公开(公告)号：US4630086A

公开(公告)日：1986-12-16

申请号：US535233

申请日：1983-09-23

申请人： Nobuyuki Sato ,  Kyotake Uchiumi ,  Shinji Nabetani ,  Ken Uchida

发明人： Nobuyuki Sato ,  Kyotake Uchiumi ,  Shinji Nabetani ,  Ken Uchida

IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L27/02 ,  H01L29/34

CPC分类号： G11C16/0433 ,  G11C16/0466 ,  H01L29/7883

摘要： A nonvolatile memory which has both the merits of a floating gate type EEPROM and an MNOS type EEPROM and which can be written into and erased with low voltages is disclosed. Each memory element in the nonvolatile memory has a floating gate, a control gate, a gate insulator film between a semiconductor body and the floating gate, and an inter-layer insulator film between the control gate and the floating gate. The gate insulator film is made up of a very thin SiO.sub.2 film and a thin Si.sub.3 N.sub.4 film formed thereon. The charge centroid of charges injected for storing data lies within the floating gate, not within the Si.sub.3 N.sub.4 film.

摘要翻译： 公开了一种非易失性存储器，其具有浮动型EEPROM和MNOS型EEPROM的优点，并且能够以低电压写入和擦除。 非易失性存储器中的每个存储元件具有浮置栅极，控制栅极，半导体主体和浮置栅极之间的栅极绝缘膜，以及控制栅极和浮动栅极之间的层间绝缘膜。 栅极绝缘膜由非常薄的SiO 2膜和形成在其上的薄的Si 3 N 4膜构成。 注入用于存储数据的电荷的电荷重心位于浮动栅极内，而不在Si3N4膜内。

公开(公告)号：US09251919B2

公开(公告)日：2016-02-02

申请号：US13993227

申请日：2011-12-13

申请人： Chikako Iwaki ,  Tatsumi Ikeda ,  Tetsuzo Yamamoto ,  Masanobu Watanabe ,  Satoru Abe ,  Ken Uchida ,  Hisaki Sato ,  Ken Okuda ,  Kiichi Ito

发明人： Chikako Iwaki ,  Tatsumi Ikeda ,  Tetsuzo Yamamoto ,  Masanobu Watanabe ,  Satoru Abe ,  Ken Uchida ,  Hisaki Sato ,  Ken Okuda ,  Kiichi Ito

IPC分类号： G21C13/00 ,  G21C15/02 ,  G21C13/02

CPC分类号： G21C15/02 ,  G21C5/10 ,  G21C13/02 ,  Y02E30/32

摘要： The pressurized water reactor according an embodiment comprises: a cylindrical reactor pressure vessel (1) to which inlet nozzles are connected; fuel assemblies which are contained within the reactor pressure vessel (1); a cylindrical reactor core barrel (3) which surrounds the fuel assemblies and forms an annular downcomer (6) between the reactor core barrel (3) and the inner surface of the reactor pressure vessel (1); and radial supports. The radial supports are supports which are arranged below the downcomer (6) at intervals in the circumferential direction, each has vertical flow path formed therein, and position the reactor core barrel (3) and the reactor pressure vessel (1). The radial supports each has, for example, a flow path-equipped radial keys (21) and a key groove member (40).

摘要翻译： 根据一个实施方案的加压水反应器包括：连接入口喷嘴的圆柱形反应器压力容器（1）; 包含在反应堆压力容器（1）内的燃料组件; 围绕燃料组件并在反应堆芯筒（3）和反应堆压力容器（1）的内表面之间形成环形降液管（6）的圆柱形反应堆芯筒（3）; 和径向支撑。 径向支撑件是沿圆周方向间隔地设置在降液管（6）下方的支撑件，每个都具有形成在其中的垂直流动通道，并且将反应堆堆芯筒（3）和反应堆压力容器（1）定位。 径向支撑件各自具有例如具有流动路径的径向键（21）和键槽构件（40）。

公开(公告)号：US20140037038A1

公开(公告)日：2014-02-06

申请号：US13980145

申请日：2012-01-18

申请人： Ken Uchida ,  Ken Okuda ,  Kazuyoshi Aoki ,  Hiroshi Ikeda ,  Chikako Iwaki ,  Tetsuzo Yamamoto

发明人： Ken Uchida ,  Ken Okuda ,  Kazuyoshi Aoki ,  Hiroshi Ikeda ,  Chikako Iwaki ,  Tetsuzo Yamamoto

IPC分类号： G21C15/02

CPC分类号： G21C15/02 ,  G21C1/086 ,  Y02E30/32

摘要： A pressurized water reactor comprises a reactor pressure vessel (11), a cylindrical core barrel (13), a core disposed in the core barrel (13), a lower core support plate (17), and a cylindrical porous plate (31). The core barrel (13) is provided in the reactor pressure vessel (11) and forms, with the inner side surface of the reactor pressure vessel (11), an annular downcomer (14) therebetween. The lower core support plate (17) is provided under the core so as to extend horizontally, and a large number of upward flow holes (80) are formed therein. The cylindrical porous plate (31) demarcates a lower plenum (16) and a bottom part of the downcomer (14), and a plurality of inward flow holes (83) that serve as flow paths from the bottom part of the downcomer (14) to the lower plenum (16) are formed therein. The inward flow holes (83) are inclined upward to the lower plenum (16) on the side on which the inward flow holes are open to the lower plenum (16).

摘要翻译： 加压水反应器包括反应堆压力容器（11），圆筒形芯筒（13），设置在芯筒（13）中的芯，下芯支撑板（17）和圆柱形多孔板（31）。 芯筒（13）设置在反应堆压力容器（11）中并与反应堆压力容器（11）的内侧表面形成在其间的环形降液管（14）。 下芯体支撑板（17）设置在芯部下方以水平延伸，并且在其中形成大量向上的流动孔（80）。 圆柱形多孔板（31）划分下降管（16）和下降管（14）的底部，以及多个向内流动孔（83），其用作从降液管（14）的底部的流动路径， 到下部通气室（16）。 向内的流通孔（83）向内侧流通孔向下部通气室（16）开放的一侧向下倾斜到下部通气室（16）。

公开(公告)号：US08076231B2

公开(公告)日：2011-12-13

申请号：US12401704

申请日：2009-03-11

申请人： Masumi Saitoh ,  Ken Uchida

发明人： Masumi Saitoh ,  Ken Uchida

IPC分类号： H01L21/4763

CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

摘要： A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.

摘要翻译： 提供了根据侧面取向和载流子极性优化的应变方向的FinFET和纳米线晶体管，以及用于实现其的SMT引入制造方法。 半导体器件包括具有半导体衬底的pMISFET，形成在衬底上部的矩形固体半导体层，具有平行于衬底的主平面的顶表面和垂直于衬底的（100）面的侧面 基板的主平面，形成在矩形半导体层中的沟道区，至少形成在矩形层的侧面上的栅极绝缘膜，栅极绝缘膜上的栅电极和形成在矩形半导体层中的源/漏区， 在其间插入通道区域。 通道区域在与基板主平面垂直的方向上施加压缩应变。 还公开了该装置的制造方法。

公开(公告)号：US20080315183A1

公开(公告)日：2008-12-25

申请号：US12052229

申请日：2008-03-20

申请人： Atsuhiro KINOSHITA ,  Yoshifumi Nishi ,  Ken Uchida ,  Junji Koga

发明人： Atsuhiro KINOSHITA ,  Yoshifumi Nishi ,  Ken Uchida ,  Junji Koga

IPC分类号： H01L29/12 ,  H01L21/336

CPC分类号： H01L51/105 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0512 ,  H01L51/0541 ,  H01L51/0545

摘要： A high-performance semiconductor device having a channel region structured from a carbon nanotube (CNT) for reducing or minimizing a drain leakage current is provided. This semiconductor device includes, in addition to the CNT-formed channel region, a gate electrode formed to overlie the channel region with a gate insulation film sandwiched therebetween, and a pair of source and drain regions interposing the channel region therebetween. The source and drain regions have portions in contact with the channel region, which portions are made of a specific semiconductor material that is wider in energy band gap than the channel region.

摘要翻译： 提供了一种具有由碳纳米管（CNT）构成的沟道区，用于降低或最小化漏极漏电流的高性能半导体器件。 除了CNT形成的沟道区域之外，该半导体器件还包括形成为覆盖沟道区域的栅电极，其间夹有栅极绝缘膜，并且在其间插入沟道区域的一对源极和漏极区域。 源极区和漏极区具有与沟道区接触的部分，这些部分由能量带隙比通道区宽的特定半导体材料制成。

公开(公告)号：US07111029B2

公开(公告)日：2006-09-19

申请号：US10235827

申请日：2002-09-06

申请人： Shinobu Fujita ,  Ken Uchida ,  Ryuji Ohba ,  Junji Koga

发明人： Shinobu Fujita ,  Ken Uchida ,  Ryuji Ohba ,  Junji Koga

IPC分类号： G06F1/02

CPC分类号： H04L9/0861 ,  G06F7/588

摘要： A random number generating circuit can generate random numbers with high randomness, and can be made as a compact integrated circuit. The random number generating circuit includes an uncertain logic circuit having a flip-flop type logic circuit that gives digital output values not determined definitely by a digital input value, and an equalizing circuit having an exclusive OR operating circuit for equalizing appearance frequencies of “0” and “1” in the digital output values output from the uncertain logic circuit.

公开(公告)号：US20100213533A1

公开(公告)日：2010-08-26

申请号：US12773967

申请日：2010-05-05

申请人： Masumi SAITOH ,  Ken Uchida

发明人： Masumi SAITOH ,  Ken Uchida

IPC分类号： H01L29/788

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L29/165 ,  H01L29/7881

摘要： A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.

摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 源极区域和漏极区域，形成在半导体衬底中以便彼此分离; 在所述半导体衬底上形成在所述源极区域和所述漏极区域之间的第一绝缘膜; 形成在所述第一绝缘膜上并具有延伸应变的半导体导电材料层的浮动电极; 形成在浮置电极上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制电极。 浮动电极的延伸应变随着位置从第二绝缘膜向第一绝缘膜前进而逐渐变小，浮动电极在浮动电极和第二绝缘膜之间的界面具有0.01％以上的延伸应变， 并且在浮动电极和第一绝缘膜之间的界面处具有小于0.01％的延伸应变。

公开(公告)号：US07781274B2

公开(公告)日：2010-08-24

申请号：US12210328

申请日：2008-09-15

申请人： Yukio Nakabayashi ,  Ken Uchida

发明人： Yukio Nakabayashi ,  Ken Uchida

IPC分类号： H01L21/00

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： A multi-gate field effect transistor includes: a plurality of semiconductor layers arranged in parallel on a substrate; source and drain regions formed in each of the semiconductor layers; channel regions each provided between the source region and the drain region in each of the semiconductor layers; protection films each provided on an upper face of each of the channel regions; gate insulating films each provided on both side faces of each of the channel regions; a plurality of gate electrodes provided on both side faces of each of the channel regions so as to interpose the gate insulating film, provided above the upper face of each of the channel region so as to interpose the protection film, and containing a metal element; a connecting portion connecting upper faces of the gate electrodes; and a gate wire connected to the connecting portion.

摘要翻译： 多栅极场效应晶体管包括：平行布置在衬底上的多个半导体层; 形成在每个半导体层中的源区和漏区; 沟道区域，每个沟道区域设置在每个半导体层中的源极区域和漏极区域之间; 保护膜分别设置在每个通道区域的上表面上; 栅极绝缘膜各自设置在每个沟道区域的两个侧面上; 设置在每个沟道区域的两个侧面上的多个栅电极，以便设置在每个沟道区域的上表面上方的栅极绝缘膜，以便插入保护膜，并且容纳金属元件; 连接所述栅电极的上表面的连接部; 以及连接到连接部分的栅极线。

公开(公告)号：US07605422B2

公开(公告)日：2009-10-20

申请号：US11846830

申请日：2007-08-29

申请人： Masumi Saitoh ,  Ken Uchida

发明人： Masumi Saitoh ,  Ken Uchida

IPC分类号： H01L29/792

CPC分类号： H01L29/4234 ,  H01L21/845 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

摘要： A semiconductor device capable of realizing low-voltage drivability and large storage capacity (miniaturization) by achieving large threshold voltage shifts and long retention time while at the same time suppressing variations in characteristics among memory cells is disclosed. The device includes a semiconductor memory cell having a channel region formed in a semiconductor substrate, a tunnel insulator film on the channel region, a charge storage insulator film on the tunnel insulator film, a control dielectric film on the charge storage film, a control electrode on the control dielectric film, and source/drain regions at opposite ends of the channel region. The memory cell's channel region has a cross-section at right angles to a direction along the channel length, the width W and height H of which are each less than or equal to 10 nm.

摘要翻译： 公开了一种半导体器件，其能够通过实现大的阈值电压偏移和长的保持时间来实现低电压驱动性和大的存储容量（小型化），同时抑制存储器单元之间的特性变化。 该器件包括半导体存储单元，其具有形成在半导体衬底中的沟道区，沟道区上的隧道绝缘膜，隧道绝缘膜上的电荷存储绝缘膜，电荷存储膜上的控制电介质膜，控制电极 在控制电介质膜上，以及在沟道区的相对端处的源/漏区。 存储单元的沟道区域具有与沿着沟道长度的方向成直角的横截面，其宽度W和高度H都小于或等于10nm。

公开(公告)号：US06787795B2

公开(公告)日：2004-09-07

申请号：US09990362

申请日：2001-11-23

申请人： Ken Uchida ,  Junji Koga ,  Ryuji Ohba

发明人： Ken Uchida ,  Junji Koga ,  Ryuji Ohba

IPC分类号： H01L2906

CPC分类号： B82Y10/00 ,  H01L29/7888 ,  H01L49/006 ,  H03K19/08

摘要： A logic apparatus having first and second single-electron devices connected serially or in parallel. Each of the single-electron devices includes a conductive island insulatively disposed between two tunnel barriers, which separate the conductive island from respective source/drain electrodes. A first charge storage region is insulatively disposed over and under the conductive island and a gate electrode, respectively. When charges are accumulated in the charge storage region, a Coulomb oscillation of the respective device is shifted by a half-period from the Coulomb oscillation that results when no charge has accumulated therein.

摘要翻译： 具有串联或并联连接的第一和第二单电子器件的逻辑器件。 每个单电子器件包括绝缘地设置在两个隧道势垒之间的导电岛，其将导电岛与相应的源/漏电极分离。 第一电荷存储区分别绝缘地设置在导电岛和栅电极之上和之下。 当在电荷存储区域中累积电荷时，各器件的库仑振荡从库仑振荡偏移了半周期，当没有电荷累积时产生库仑振荡。