公开(公告)号：US20080149991A1

公开(公告)日：2008-06-26

申请号：US11859142

申请日：2007-09-21

申请人： Masumi SAITOH ,  Ken UCHIDA

发明人： Masumi SAITOH ,  Ken UCHIDA

IPC分类号： H01L29/788 ,  H01L21/3205

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L29/165 ,  H01L29/7881

摘要： A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.

摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 源极区域和漏极区域，形成在半导体衬底中以便彼此分离; 在所述半导体衬底上形成在所述源极区域和所述漏极区域之间的第一绝缘膜; 形成在所述第一绝缘膜上并具有延伸应变的半导体导电材料层的浮动电极; 形成在浮置电极上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制电极。 浮动电极的延伸应变随着位置从第二绝缘膜向第一绝缘膜前进而逐渐变小，浮动电极在浮动电极和第二绝缘膜之间的界面具有0.01％以上的延伸应变， 并且在浮动电极和第一绝缘膜之间的界面处具有小于0.01％的延伸应变。

公开(公告)号：US20080054346A1

公开(公告)日：2008-03-06

申请号：US11846830

申请日：2007-08-29

申请人： Masumi SAITOH ,  Ken Uchida

发明人： Masumi SAITOH ,  Ken Uchida

IPC分类号： H01L29/792

CPC分类号： H01L29/4234 ,  H01L21/845 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

摘要： A semiconductor device capable of realizing low-voltage drivability and large storage capacity (miniaturization) by achieving large threshold voltage shifts and long retention time while at the same time suppressing variations in characteristics among memory cells is disclosed. The device includes a semiconductor memory cell having a channel region formed in a semiconductor substrate, a tunnel insulator film on the channel region, a charge storage insulator film on the tunnel insulator film, a control dielectric film on the charge storage film, a control electrode on the control dielectric film, and source/drain regions at opposite ends of the channel region. The memory cell's channel region has a cross-section at right angles to a direction along the channel length, the width W and height H of which are each less than or equal to 10 nm.

摘要翻译： 公开了一种半导体器件，其能够通过实现大的阈值电压偏移和长的保持时间来实现低电压驱动性和大的存储容量（小型化），同时抑制存储器单元之间的特性的变化。 该器件包括半导体存储单元，其具有形成在半导体衬底中的沟道区，沟道区上的隧道绝缘膜，隧道绝缘膜上的电荷存储绝缘膜，电荷存储膜上的控制电介质膜，控制电极 在控制电介质膜上，以及在沟道区的相对端处的源/漏区。 存储单元的沟道区域具有与沿着沟道长度的方向成直角的横截面，其宽度W和高度H都小于或等于10nm。

公开(公告)号：US20120037994A1

公开(公告)日：2012-02-16

申请号：US13283264

申请日：2011-10-27

申请人： Masumi SAITOH ,  Ken UCHIDA

发明人： Masumi SAITOH ,  Ken UCHIDA

IPC分类号： H01L27/092

CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

摘要： A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.

摘要翻译： 提供了根据侧面取向和载流子极性优化的应变方向的FinFET和纳米线晶体管以及用于实现其的SMT引入制造方法。 半导体器件包括具有半导体衬底的pMISFET，形成在衬底上部的矩形固体半导体层，具有平行于衬底的主平面的顶表面和垂直于衬底的（100）面的侧面 基板的主平面，形成在矩形半导体层中的沟道区，至少形成在矩形层的侧面上的栅极绝缘膜，栅极绝缘膜上的栅电极和形成在矩形半导体层中的源/漏区， 在其间插入通道区域。 通道区域在与基板主平面垂直的方向上施加压缩应变。 还公开了该装置的制造方法。

公开(公告)号：US20090242990A1

公开(公告)日：2009-10-01

申请号：US12401704

申请日：2009-03-11

申请人： Masumi SAITOH ,  Ken UCHIDA

发明人： Masumi SAITOH ,  Ken UCHIDA

IPC分类号： H01L27/092 ,  H01L21/28 ,  H01L21/20

CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

摘要： A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.

摘要翻译： 提供了根据侧面取向和载流子极性优化的应变方向的FinFET和纳米线晶体管，以及用于实现其的SMT引入制造方法。 半导体器件包括具有半导体衬底的pMISFET，形成在衬底上部的矩形固体半导体层，具有平行于衬底的主平面的顶表面和垂直于衬底的（100）面的侧面 基板的主平面，形成在矩形半导体层中的沟道区，至少形成在矩形层的侧面上的栅极绝缘膜，栅极绝缘膜上的栅电极和形成在矩形半导体层中的源/漏区， 在其间插入通道区域。 通道区域在与基板主平面垂直的方向上施加压缩应变。 还公开了该装置的制造方法。

公开(公告)号：US20100213533A1

公开(公告)日：2010-08-26

申请号：US12773967

申请日：2010-05-05

申请人： Masumi SAITOH ,  Ken Uchida

发明人： Masumi SAITOH ,  Ken Uchida

IPC分类号： H01L29/788

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L29/165 ,  H01L29/7881

摘要： A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.

摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 源极区域和漏极区域，形成在半导体衬底中以便彼此分离; 在所述半导体衬底上形成在所述源极区域和所述漏极区域之间的第一绝缘膜; 形成在所述第一绝缘膜上并具有延伸应变的半导体导电材料层的浮动电极; 形成在浮置电极上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制电极。 浮动电极的延伸应变随着位置从第二绝缘膜向第一绝缘膜前进而逐渐变小，浮动电极在浮动电极和第二绝缘膜之间的界面具有0.01％以上的延伸应变， 并且在浮动电极和第一绝缘膜之间的界面处具有小于0.01％的延伸应变。

公开(公告)号：US20120146053A1

公开(公告)日：2012-06-14

申请号：US13237697

申请日：2011-09-20

申请人： Masumi SAITOH ,  Toshinori Numata ,  Yukio Nakabayashi ,  Kensuke Ota

发明人： Masumi SAITOH ,  Toshinori Numata ,  Yukio Nakabayashi ,  Kensuke Ota

IPC分类号： H01L29/161 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7843

摘要： A semiconductor device according to an embodiment includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, first gate sidewalls formed on both sides of the gate electrode, and a source/drain semiconductor layer formed on the semiconductor substrate to sandwich the first gate sidewalls with the gate electrode. Further, second gate sidewalls are provided on the first gate sidewalls and the source/drain semiconductor layer at both sides of the gate electrode, wherein the boundary of each of the second gate sidewalls with each of the first gate sidewalls is terminated at the side surface of the gate electrode, and each of the second gate sidewalls has a smaller Young's modulus and a lower dielectric constant than each of the first gate sidewalls.

摘要翻译： 根据实施例的半导体器件包括半导体衬底，形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，形成在栅电极两侧的第一栅极侧壁和源极/漏极半导体 层，形成在半导体衬底上，以与栅电极夹住第一栅极侧壁。 此外，第二栅极侧壁设置在栅电极两侧的第一栅极侧壁和源极/漏极半导体层上，其中每个第二栅极侧壁与每个第一栅极侧壁的边界在侧表面终止 并且每个第二栅极侧壁具有比每个第一栅极侧壁更小的杨氏模量和更低的介电常数。

公开(公告)号：US20130240828A1

公开(公告)日：2013-09-19

申请号：US13729959

申请日：2012-12-28

申请人： Kensuke OTA ,  Toshinori NUMATA ,  Masumi SAITOH ,  Chika TANAKA ,  Yusuke HIGASHI

发明人： Kensuke OTA ,  Toshinori NUMATA ,  Masumi SAITOH ,  Chika TANAKA ,  Yusuke HIGASHI

IPC分类号： H01L29/32

CPC分类号： H01L29/32 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78696

摘要： A semiconductor device according to embodiments includes a semiconductor substrate, a buried insulating layer which is formed on the semiconductor substrate, a semiconductor layer which is formed on the buried insulating layer and includes a narrow portion and two wide portions which are larger than the narrow portion in width and are respectively connected to one end and the other end of the narrow portion, a gate insulating film which is formed on a side surface of the narrow portion, and a gate electrode formed on the gate insulating film. The impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the narrow portion, and the impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the semiconductor substrate directly below the wide portion.

摘要翻译： 根据实施例的半导体器件包括半导体衬底，形成在半导体衬底上的掩埋绝缘层，形成在掩埋绝缘层上并且包括狭窄部分和比窄部分大的两个宽部分的半导体层 并且分别连接到窄部分的一端和另一端，形成在窄部分的侧表面上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。 直接在窄部下方的半导体衬底的杂质浓度高于窄部分的杂质浓度，并且直接在窄部下方的半导体衬底的杂质浓度高于直接在宽度以下的半导体衬底的杂质浓度 一部分。

公开(公告)号：US20120282743A1

公开(公告)日：2012-11-08

申请号：US13487295

申请日：2012-06-04

申请人： Masumi SAITOH ,  Toshinori Numata ,  Yukio Nakabayashi

发明人： Masumi SAITOH ,  Toshinori Numata ,  Yukio Nakabayashi

IPC分类号： H01L21/336

CPC分类号： H01L27/0207 ,  H01L21/266 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66628 ,  H01L29/785

摘要： In a semiconductor device manufacturing method, a first semiconductor region which includes a narrow portion and a wide portion is formed in an upper portion of a semiconductor substrate, a gate insulating film is formed on at least side surfaces of the narrow portion, a gate electrode is formed on the gate insulating film, a mask pattern that covers the wide portion is formed, ion implantation of an impurity is performed with the mask pattern as a mask to form an extension impurity region in the narrow portion, the mask pattern is removed, a heat treatment is performed to activate the impurity, a gate sidewall is formed on a side surface of the gate electrode, epitaxial growth of a semiconductor film is performed on the narrow portion and the wide portion after the formation of the gate sidewall, and source-drain regions is formed on both sides of the gate electrode.

摘要翻译： 在半导体器件制造方法中，在半导体衬底的上部形成包括窄部分和宽部分的第一半导体区域，在所述窄部分的至少侧表面上形成栅极绝缘膜，栅电极 形成在栅极绝缘膜上，形成覆盖该宽部的掩模图形，利用掩模图案作为掩模进行杂质的离子注入，以在狭窄部分形成延伸杂质区，除去掩模图案， 执行热处理以激活杂质，在栅电极的侧表面上形成栅极侧壁，在形成栅极侧壁的狭窄部分和宽部分之后进行半导体膜的外延生长，源 在栅电极的两侧形成有引线区域。

公开(公告)号：US20120299100A1

公开(公告)日：2012-11-29

申请号：US13415592

申请日：2012-03-08

申请人： Kensuke OTA ,  Toshinori NUMATA ,  Masumi SAITOH ,  Chika TANAKA

发明人： Kensuke OTA ,  Toshinori NUMATA ,  Masumi SAITOH ,  Chika TANAKA

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/786 ,  H01L29/00 ,  H01L29/785 ,  H01L29/78696

摘要： A semiconductor device of an embodiment includes: an insulating film including: a first region extending in a first direction; second and third regions arranged at a distance from each other; and fourth and fifth regions each having a concave shape, the fourth and fifth regions each having a smaller film thickness than a film thickness of each of the first through third regions; a semiconductor layer formed in a direction from the fourth region toward the fifth region, the semiconductor layer having a smaller width than a width of each of source and drain regions, the semiconductor layer being connected to the source and drain regions; a gate electrode placed on the opposite side of a gate insulating film from the semiconductor layer on the first region; and a gate sidewall formed on a side face of the gate electrode.

摘要翻译： 实施例的半导体器件包括：绝缘膜，包括：沿第一方向延伸的第一区域; 第二和第三区域彼此相隔一定距离; 第四和第五区域各自具有凹形形状，第四和第五区域各自具有比每个第一至第三区域的膜厚度更薄的膜厚度; 在从第四区域朝向第五区域的方向上形成的半导体层，所述半导体层的宽度小于源极和漏极区域的宽度，所述半导体层连接到所述源极和漏极区域; 栅极电极，位于栅极绝缘膜的与第一区域上的半导体层相反的一侧; 以及形成在栅电极的侧面上的栅极侧壁。

公开(公告)号：US20120273747A1

公开(公告)日：2012-11-01

申请号：US13458042

申请日：2012-04-27

申请人： Masumi SAITOH ,  Toshinori NUMATA ,  Kiwamu SAKUMA ,  Haruka KUSAI ,  Takayuki ISHIKAWA

发明人： Masumi SAITOH ,  Toshinori NUMATA ,  Kiwamu SAKUMA ,  Haruka KUSAI ,  Takayuki ISHIKAWA

IPC分类号： H01L27/26 ,  H01L21/8239 ,  H01L27/088

CPC分类号： H01L21/823431 ,  H01L27/101 ,  H01L27/1211 ,  H01L27/2409 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor device includes a fin type stacked layer structure which has first to third semiconductor layers, and first to third layer select transistors to select one of the first to third semiconductor layers. The second layer select transistor is normally on in the second semiconductor layer, and is controlled to be on or off in the first and third semiconductor layers. A channel region of the second semiconductor layer which is covered with a gate electrode of the second layer select transistor has a metal silicide.

摘要翻译： 根据一个实施例，半导体器件包括具有第一至第三半导体层的鳍式堆叠层结构以及选择第一至第三半导体层之一的第一至第三层选择晶体管。 第二层选择晶体管通常在第二半导体层中导通，并且在第一和第三半导体层中被控制为导通或截止。 被第二层选择晶体管的栅电极覆盖的第二半导体层的沟道区域具有金属硅化物。