公开(公告)号：US06503787B1

公开(公告)日：2003-01-07

申请号：US09631546

申请日：2000-08-03

申请人： Seungmoo Choi

发明人： Seungmoo Choi

IPC分类号： H01L218238

CPC分类号： H01L21/823475 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor device, formed on a semiconductor wafer, comprising a tub, first and second active areas, and an interconnect. In one aspect of the present invention, the tub is formed in the substrate of the semiconductor wafer and first and second active areas are in contact with the tub. In one advantageous embodiment, the interconnect is formed in the tub and is in electrical contact with the first and second active areas. The interconnect extends from the first active area to the second active area to electrically connect the first and second active areas.

摘要翻译： 本发明提供一种形成在半导体晶片上的半导体器件，包括一个第一和第二有源区以及互连。 在本发明的一个方面，在半导体晶片的衬底中形成桶，并且第一和第二有源区与桶接触。 在一个有利的实施例中，互连件形成在桶中并且与第一和第二有效区域电接触。 互连从第一有源区延伸到第二有源区，以电连接第一和第二有源区。

公开(公告)号：US06483144B2

公开(公告)日：2002-11-19

申请号：US09451054

申请日：1999-11-30

申请人： Seungmoo Choi

发明人： Seungmoo Choi

IPC分类号： H01L29788

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L27/105 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device and method of forming same is disclosed and includes a silicon substrate having a field oxide region and spaced active region. First and second self-aligned contact window openings are associated with a respective field oxide region and active region. A dummy polysilicon landing pad is formed over the field oxide region and formed below the first self-aligned contact window opening. An operative polysilicon landing pad is formed above the dummy landing pad. A silicon nitride barrier layer is also formed during the process.

摘要翻译： 公开了半导体集成电路器件及其形成方法，并且包括具有场氧化物区域和间隔开的有源区域的硅衬底。 第一和第二自对准接触窗口与相应的场氧化物区域和有源区域相关联。 虚场多晶硅着陆焊盘形成在场氧化物区域上并形成在第一自对准接触窗口下方。 在虚拟着陆板上方形成有效的多晶硅着陆焊盘。 在该过程中也形成氮化硅阻挡层。

公开(公告)号：US06376302B1

公开(公告)日：2002-04-23

申请号：US09484500

申请日：2000-01-18

申请人： Seungmoo Choi

发明人： Seungmoo Choi

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L28/91

摘要： An integrated DRAM cell comprises a DRAM capacitor and a transistor. The capacitor of the cell is formed in a first well in a dielectric layer overlying the cell transistor. The top electrode of the capacitor also serves as a barrier layer between an underlying plug in a second well in the dielectric layer. A method of forming the cell comprises the step of using a single mask for formation of the layer which acts as both the top electrode of the capacitor and the barrier layer of the second well.

摘要翻译： 集成DRAM单元包括DRAM电容器和晶体管。 电池的电容器形成在覆盖电池晶体管的电介质层中的第一阱中。 电容器的顶部电极还用作介电层中第二阱中的下面的插塞之间的阻挡层。 形成电池的方法包括使用单个掩模形成用作电容器的顶部电极和第二阱的阻挡层两者的层的步骤。

公开(公告)号：US20080144354A1

公开(公告)日：2008-06-19

申请号：US11641646

申请日：2006-12-19

申请人： Seungmoo Choi ,  Sameer Haddad

发明人： Seungmoo Choi ,  Sameer Haddad

IPC分类号： G11C11/00 ,  H01L21/22

CPC分类号： H01L27/2409 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C17/06 ,  H01L21/2256 ,  H01L27/24 ,  H01L27/2463 ,  H01L29/6609 ,  H01L29/868 ,  H01L45/1608

摘要： An electronic structure includes a resistive memory device, and a P-I-N diode in operative association with the resistive memory device. A plurality of such electronic structures are used in a resistive memory array, with the P-I-N diodes functioning as select devices in the array. Methods are provided for fabricating such resistive memory device-P-I-N diode structures.

摘要翻译： 电子结构包括电阻性存储器件和与电阻式存储器件可操作地相关联的P-I-N二极管。 在电阻式存储器阵列中使用多个这样的电子结构，其中P-I-N二极管用作阵列中的选择器件。 提供了制造这种电阻式存储器件-P-I-N二极管结构的方法。

公开(公告)号：US06586310B1

公开(公告)日：2003-07-01

申请号：US09384631

申请日：1999-08-27

申请人： Seungmoo Choi ,  Amal M. Hamad ,  Felix Llevada ,  Vivek Saxena ,  Paul Yih

发明人： Seungmoo Choi ,  Amal M. Hamad ,  Felix Llevada ,  Vivek Saxena ,  Paul Yih

IPC分类号： H01L2702

CPC分类号： H01L27/11 ,  H01L27/1112

摘要： The present invention provides a method of manufacturing a resistor for use in a memory element and a semiconductor device employing the resistor. The method of manufacturing may comprise forming a dielectric layer over an active region of a semiconductor wafer and forming a resistive layer on the dielectric layer. The resistive layer comprises a compound wherein a first element of the compound is a Group III or Group IV element and a second element of the compound is a Group IV or Group V element. The method further comprises connecting an electrical interconnect structure to the resistive layer that electrically connects the resistive layer to the active region.

摘要翻译： 本发明提供一种制造用于存储元件的电阻器和采用该电阻器的半导体器件的方法。 制造方法可以包括在半导体晶片的有源区上形成电介质层，并在电介质层上形成电阻层。 电阻层包括化合物，其中化合物的第一元素是III族或IV族元素，该化合物的第二元素是IV族或V族元素。 该方法还包括将电互连结构连接到将电阻层电连接到有源区的电阻层。

公开(公告)号：US06320244B1

公开(公告)日：2001-11-20

申请号：US09388682

申请日：1999-09-02

申请人： Glenn B. Alers ,  Seungmoo Choi ,  Sailesh Mansinh Merchant ,  Pradip Kumar Roy

发明人： Glenn B. Alers ,  Seungmoo Choi ,  Sailesh Mansinh Merchant ,  Pradip Kumar Roy

IPC分类号： H01L2900

CPC分类号： H01L27/1085 ,  H01L21/76807 ,  H01L28/82 ,  H01L28/90 ,  H01L28/91

摘要： An integrated circuit device includes a dielectric layer having an opening therein, and a capacitor comprising in stacked relation a lower electrode lining the opening, a capacitor dielectric layer adjacent the lower electrode, and an upper electrode adjacent the capacitor dielectric layer. The capacitor has a substantially planar upper surface substantially flush with adjacent upper surface portions of the dielectric layer. Additionally, the edges of the lower electrode and the capacitor dielectric layer preferably terminate at the upper surface of the capacitor. Also, the capacitor dielectric may include a high-k, high quality and low leakage dielectric, and which prevents the reduction of the capacitor dielectric by the metal of the upper and lower metal electrodes.

摘要翻译： 一种集成电路器件，包括其中具有开口的电介质层，以及电容器，其包括堆叠关系中位于开口的下电极，邻近下电极的电容器电介质层和与电容器电介质层相邻的上电极。 电容器具有基本平坦的上表面，其基本上与电介质层的相邻上表面部分齐平。 此外，下电极和电容器电介质层的边缘优选终止于电容器的上表面。 此外，电容器电介质可以包括高k，高质量和低泄漏电介质，并且防止电容器电介质被上下金属电极的金属减少。

公开(公告)号：US06274409B1

公开(公告)日：2001-08-14

申请号：US09484759

申请日：2000-01-18

申请人： Seungmoo Choi

发明人： Seungmoo Choi

IPC分类号： H01L2182

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823475 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for making a semiconductor device includes forming a plurality of transistors in a semiconductor substrate, forming a first dielectric layer overlying the semiconductor substrate, and selectively etching the first dielectric layer to form a first opening exposing a first transistor portion and a second transistor portion. Conducting material is deposited into the first opening to define a merged contact between the first transistor portion and the second transistor portion. The method further includes forming a second dielectric layer overlying the first dielectric layer and the merged contact, and selectively etching the second dielectric layer to form a second opening exposing the merged contact, and while selectively etching the second and first dielectric layers to form a third opening exposing a source/drain region of a third transistor to define a self-aligned contact. Conducting material is deposited into the second opening to define a first via with the merged contact, and conducting material is also deposited into the third opening to define a second via with the source/drain region of the third transistor. The self-aligned contact and the merged contact are formed using a reduced number of masks and masking steps.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底中形成多个晶体管，形成覆盖半导体衬底的第一电介质层，并选择性地蚀刻第一电介质层以形成暴露第一晶体管部分和第二晶体管部分的第一开口 。 将导电材料沉积到第一开口中以限定第一晶体管部分和第二晶体管部分之间的合并接触。 该方法还包括形成覆盖第一电介质层和合并接触的第二电介质层，并且选择性地蚀刻第二电介质层以形成暴露合并的接触的第二开口，以及在选择性地刻蚀第二和第一电介质层以形成第三电介质层 打开暴露第三晶体管的源极/漏极区域以限定自对准接触。 将导电材料沉积到第二开口中以限定具有合并的触点的第一通孔，并且导电材料也沉积到第三开口中以限定与第三晶体管的源极/漏极区域的第二通孔。 使用减少数量的掩模和掩蔽步骤形成自对准接触和合并接触。

公开(公告)号：US06215158B1

公开(公告)日：2001-04-10

申请号：US09150529

申请日：1998-09-10

申请人： Seungmoo Choi

发明人： Seungmoo Choi

IPC分类号： H01L2940

CPC分类号： H01L21/823475 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor device, formed on a semiconductor wafer, comprising a tub, first and second active areas, and an interconnect. In one aspect of the present invention, the tub is formed in the substrate of the semiconductor wafer and first and second active areas are in contact with the tub. In one advantageous embodiment, the interconnect is formed in the tub and is in electrical contact with the first and second active areas. The interconnect extends from the first active area to the second active area to electrically connect the first and second active areas.

摘要翻译： 本发明提供一种形成在半导体晶片上的半导体器件，包括一个第一和第二有源区以及互连。 在本发明的一个方面，在半导体晶片的衬底中形成桶，并且第一和第二有源区与桶接触。 在一个有利的实施例中，互连件形成在桶中并且与第一和第二有效区域电接触。 互连从第一有源区延伸到第二有源区，以电连接第一和第二有源区。

公开(公告)号：US07989328B2

公开(公告)日：2011-08-02

申请号：US11641646

申请日：2006-12-19

申请人： Seungmoo Choi ,  Sameer Haddad

发明人： Seungmoo Choi ,  Sameer Haddad

IPC分类号： H01L21/38

CPC分类号： H01L27/2409 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C17/06 ,  H01L21/2256 ,  H01L27/24 ,  H01L27/2463 ,  H01L29/6609 ,  H01L29/868 ,  H01L45/1608

摘要： An electronic structure includes a resistive memory device, and a P-I-N diode in operative association with the resistive memory device. A plurality of such electronic structures are used in a resistive memory array, with the P-I-N diodes functioning as select devices in the array. Methods are provided for fabricating such resistive memory device-P-I-N diode structures.

摘要翻译： 电子结构包括电阻性存储器件和与电阻式存储器件可操作地相关联的P-I-N二极管。 在电阻式存储器阵列中使用多个这样的电子结构，其中P-I-N二极管用作阵列中的选择器件。 提供了制造这种电阻式存储器件-P-I-N二极管结构的方法。

公开(公告)号：US07563669B2

公开(公告)日：2009-07-21

申请号：US11383670

申请日：2006-05-16

申请人： Sailesh Chittipeddi ,  Seungmoo Choi

发明人： Sailesh Chittipeddi ,  Seungmoo Choi

IPC分类号： H01L21/8242 ,  H01L21/108

CPC分类号： H01L28/40 ,  H01L27/1087 ,  H01L27/11

摘要： An integrated circuit device having a capacitor structure. In one form of the invention, an integrated circuit device includes a capacitor structure formed along a surface of a semiconductor layer. The capacitor structure includes a region formed in the semiconductor surface, a layer of dielectric material formed along a trench wall of the trench region and a first layer of doped polysilicon formed over the layer of dielectric material in the trench region. The capacitor structure further includes a second layer of doped polysilicon formed over the first layer of polysilicon.

摘要翻译： 一种具有电容器结构的集成电路器件。 在本发明的一种形式中，集成电路器件包括沿着半导体层的表面形成的电容器结构。 电容器结构包括形成在半导体表面中的区域，沿着沟槽区域的沟槽壁形成的介电材料层和在沟槽区域中形成在电介质材料层上的第一掺杂多晶硅层。 电容器结构还包括形成在第一多晶硅层上的第二掺杂多晶硅层。