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11.发明授权Integrated circuit with temperature sensor and method for heating the circuit 失效具有温度传感器的集成电路和加热电路的方法公开(公告)号：US06798706B2
公开(公告)日：2004-09-28
申请号：US10352824
申请日：2003-01-28
IPC分类号： G11C704
CPC分类号： G01K7/01
摘要： A temperature sensor is integrated together with an integrated circuit on a chip, the sensor delivering a temperature-dependent measuring signal or at least emitting a signal when the chip temperature falls below a specific prescribed value. For such an eventuality, the chip includes a special circuit device thereon, by which a current flow is generated through a provided structure of electrical conductors that keeps the temperature of the integrated circuit above a prescribed minimum temperature.
摘要翻译： 温度传感器与芯片上的集成电路集成在一起，传感器传递温度相关的测量信号，或者当芯片温度低于特定规定值时至少发出信号。 对于这样的可能性，芯片包括其上的专用电路装置，通过该电路，电流通过提供的集成电路的温度高于预定的最低温度的电导体的结构产生。
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12.发明授权公开(公告)号：US07305525B2
公开(公告)日：2007-12-04
申请号：US11132419
申请日：2005-05-19
CPC分类号： H04N21/2182 , G11C7/1018 , G11C7/103 , H04N21/23116 , H04N21/2312 , H04N21/2323
摘要： A memory system for network broadcasting applications, such as video/audio applications, has at least one memory which is divided into a plurality of addressable memory units, which have a respective dedicated output for interchanging data. The inputs of a matrix switch are connected to a respective output of a different memory unit. The matrix switch is operated such that a plurality of the memory units are connected to its output in a sequential order. A first sequence of memory units and a second sequence of memory units are connected to its output independently. This results in a memory system, which can handle a number of requests to the same memory at staggered times. The interaction of the individual memory units with the matrix switch allows a high data throughput and a short access time.
摘要翻译： 用于诸如视频/音频应用的网络广播应用的存储器系统具有至少一个存储器，其被分成多个可寻址存储器单元，其具有用于交换数据的相应的专用输出。 矩阵开关的输入端连接到不同存储器单元的相应输出端。 矩阵开关的操作使得多个存储器单元以其顺序连接到其输出。 存储单元的第一序列和第二存储单元序列独立地连接到其输出。 这导致存储器系统，其可以以交错的时间处理对相同存储器的多个请求。 单个存储器单元与矩阵开关的交互允许高数据吞吐量和短的访问时间。
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13.发明申请公开(公告)号：US20050248994A1
公开(公告)日：2005-11-10
申请号：US11132419
申请日：2005-05-19
CPC分类号： H04N21/2182 , G11C7/1018 , G11C7/103 , H04N21/23116 , H04N21/2312 , H04N21/2323
摘要： A memory system for network broadcasting applications, such as video/audio applications, has at least one memory which is divided into a plurality of addressable memory units, which have a respective dedicated output for interchanging data. The inputs of a matrix switch are connected to a respective output of a different memory unit. The matrix switch is operated such that a plurality of the memory units are connected to its output in a sequential order. A first sequence of memory units and a second sequence of memory units are connected to its output independently. This results in a memory system, which can handle a number of requests to the same memory at staggered times. The interaction of the individual memory units with the matrix switch allows a high data throughput and a short access time.
摘要翻译： 用于诸如视频/音频应用的网络广播应用的存储器系统具有至少一个存储器，其被分成多个可寻址存储器单元，其具有用于交换数据的相应的专用输出。 矩阵开关的输入端连接到不同存储器单元的相应输出端。 矩阵开关的操作使得多个存储器单元以其顺序连接到其输出。 存储单元的第一序列和第二存储单元序列独立地连接到其输出。 这导致存储器系统，其可以以交错的时间处理对相同存储器的多个请求。 单个存储器单元与矩阵开关的交互允许高数据吞吐量和短的访问时间。
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14.发明授权公开(公告)号：US06798051B2
公开(公告)日：2004-09-28
申请号：US10197793
申请日：2002-07-18
IPC分类号： H01L2302
CPC分类号： H05K1/141 , H01L25/0652 , H01L2224/48091 , H05K1/145 , H05K3/3447 , H05K2201/10287 , H05K2201/10325 , H05K2201/10522 , H05K2201/1053 , H05K2201/10689 , H01L2924/00014
摘要： An interface unit and a printed circuit board configuration includes at least two interface units for linking conventional commercially available packages of integrated circuits on a printed circuit board in a more flexible and compact way, which allows compact high-performance electronic circuits to be produced on a small surface area and with low development expenditure.
摘要翻译： 接口单元和印刷电路板配置包括至少两个接口单元，用于以更灵活和紧凑的方式将印刷电路板上的常规商业可用的集成电路封装连接起来，这使得可以在紧凑型高性能电子电路 表面积小，开发费用低。
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15.发明授权Method for integrating imperfect semiconductor memory devices in data processing apparatus 有权在数据处理装置中集成不完美的半导体存储器件的方法公开(公告)号：US06762965B2
公开(公告)日：2004-07-13
申请号：US10254694
申请日：2002-09-25
IPC分类号： G11C700
CPC分类号： G11C29/76 , G11C29/88 , G11C29/883
摘要： A method for integrating imperfect semiconductor memory devices having functional and defective memory cells into a data processing apparatus. The defective memory cells are assigned defect addresses or defect address ranges. Before a memory access of the data processing apparatus is carried out, the address of the memory access is compared with the defect addresses or defect address ranges and is recoded in the event of correspondence.
摘要翻译： 一种用于将具有功能和缺陷存储器单元的不完美半导体存储器件集成到数据处理装置中的方法。 缺陷存储单元被分配缺陷地址或缺陷地址范围。 在执行数据处理装置的存储器访问之前，将存储器访问的地址与缺陷地址或缺陷地址范围进行比较，并且在对应的情况下被重新编码。
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公开(公告)号：US06590824B2
公开(公告)日：2003-07-08
申请号：US10112521
申请日：2002-03-28
IPC分类号： G11C700
CPC分类号： G11C11/406 , G11C7/062 , G11C7/14 , G11C11/4091 , G11C11/4099
摘要： A dynamic semiconductor memory and a method for operating such a memory includes memory banks with memory cells disposed in rows, and registers associated with the memory banks for storing an address of an open, activated word line. In the event of an external refresh command, a control device causes, after the refresh operation, the state of the memory banks to be reestablished, in particular, the word line whose address was stored in the register to be reactivated. Such a purely on-chip measure increases the operating speed of the memory.
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公开(公告)号：US06876217B2
公开(公告)日：2005-04-05
申请号：US10272344
申请日：2002-10-15
CPC分类号： G11C29/40 , G11C2029/2602
摘要： To be able to test a plurality of identical semiconductor circuit devices in a particularly rapid yet reliable manner, a test method includes carrying out the tests in parallel and substantially simultaneously on the plurality of semiconductor circuit devices and driver lines—used in the process—of a test device to the semiconductor circuit devices simultaneously and jointly for all the semiconductor circuit devices. In such a case, test results are read from a plurality of input/output channels in compressed form. Furthermore, as an alternative or in addition thereto, the semiconductor circuit devices to be tested are disposed and connected up in at least one stack.
摘要翻译： 为了能够以特别快速且可靠的方式测试多个相同的半导体电路器件，测试方法包括并行并且基本上同时地在用于该过程的多个半导体电路器件和驱动器线路上执行测试 用于半导体电路装置的测试装置，同时并共同地用于所有半导体电路装置。 在这种情况下，从压缩形式的多个输入/输出通道读取测试结果。 此外，作为替代或补充，待测试的半导体电路器件被布置并连接到至少一个堆叠中。
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18.发明授权公开(公告)号：US06806121B2
公开(公告)日：2004-10-19
申请号：US10285090
申请日：2002-10-31
IPC分类号： H01L2144
CPC分类号： H01L21/76838 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to an interconnect structure for an integrated circuit (1) having a first interconnect (B1; B1′; B1″), which is composed of a plurality of interconnect sections (A11-A16; A11′-A16′; A11″-A14″) lying in a first and a second interconnect plane (M0, M1); and a second interconnect (B2; B2′; B2″), which runs adjacent to the first interconnect (B1; B1′; B1″) and which is composed of a plurality of interconnect sections (A21-A25; A21′-A25′; A21″-A23″) lying in the first and second interconnect planes (M0, M1); the first and second interconnects (B1; B1′; B1″; B2; B2′; B2″) being offset with respect to one another in the longitudinal direction in such a way that the interconnect sections (A12, A14, A16; A12′, A14′, A16′; A12″, A14″) of the first interconnect (B1; B1′; B1″) which lie in the first interconnect plane (M0) run at least in sections beside the interconnect sections (A22, A24; A22′; A24′; A21″, A23″) of the second interconnect (B2; B2′; B2″) which lie in the second interconnection plane (M1), and that the interconnect sections (A11, A13, A15; A11′, A13′, A15′; A11″, A13″) of the first interconnect (B1; B1′; B1″) which lie in the second interconnect plane (M1) run at least in sections beside the interconnect sections (A21, A23, A25; A21′, A23′, A25′; A22″) of the second interconnect (B2; B2′; B2″) which lie in the first interconnect plane (M0). The invention also provides a corresponding fabrication method.
摘要翻译： 本发明涉及具有第一互连（B1; B1'; B1“）的集成电路（1）的互连结构，其由多个互连部分（A11-A16; A11'-A16'）组成; A11“-A14”），位于第一和第二互连平面（M0，M1）中; 和与第一互连（B1; B1'; B1“）相邻的第二互连（B2; B2'; B2”），它们由多个互连部分（A21-A25; A21'- A25“; A21”-A23“），位于第一和第二互连平面（M0，M1）中; 第一和第二互连（B1; B1'; B1“; B2; B2'; B2”）在纵向方向上彼此偏移，使得互连部分（A12，A14，A16; 位于第一互连平面（M0）中的第一互连（B1; B1'; B1“）的A12'，A14'，A16'; A12”，A14“）至少在互连部分旁边 位于第二互连平面（M1）中的第二互连（B2; B2'; B2“）的位置（A22，A24; A22'; A24'; A21”，A23“）， A11，A13，A
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公开(公告)号：US06738304B2
公开(公告)日：2004-05-18
申请号：US10283992
申请日：2002-10-30
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： According to one embodiment, a dynamic memory is provided. The dynamic memory can include a memory matrix having a plurality of memory cells arranged in rows and columns. The memory cells in a row can be connected by in each case one of a plurality of word lines. The memory cells in a column can be connected by in each case one of a plurality of bit lines. The dynamic memory can also include a sense amplifier for reading data from the memory cells via the plurality of bit lines. Further, the dynamic memory can include a row address decoder and a column address decoder for generating memory-internal address in a manner dependent on a memory-external address signal. The dynamic memory can also include a sequence control device for cyclically generating refresh addresses for carrying for carrying out a refresh operation of the memory cells.
摘要翻译： 根据一个实施例，提供动态存储器。 动态存储器可以包括具有以行和列排列的多个存储器单元的存储器矩阵。 在每种情况下，可以连接多行字线中的一行中的存储单元。 列中的存储单元可以在每种情况下连接多个位线中的一个。 动态存储器还可以包括用于经由多个位线从存储器单元读取数据的读出放大器。 此外，动态存储器可以包括行地址解码器和用于以取决于存储器 - 外部地址信号的方式产生存储器内部地址的列地址解码器。 动态存储器还可以包括用于循环产生刷新地址以执行对存储器单元进行刷新操作的序列控制装置。
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公开(公告)号：US06556496B2
公开(公告)日：2003-04-29
申请号：US09941902
申请日：2001-08-29
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A semiconductor configuration is described and has a temperature sensor, which measures a temperature of a semiconductor module. The measured temperature is provided to a control unit, so that the control unit can adapt a refresh cycle in the semiconductor module to the retention time corresponding to the measured temperature.
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