公开(公告)号：US11789807B1

公开(公告)日：2023-10-17

申请号：US17301254

申请日：2021-03-30

Applicant: Amazon Technologies, Inc.

Inventor： Gal Kochavi ,  Benny Pollak ,  Sergey Kleyman ,  Itai Avron

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/079 ,  G06F11/0751

Abstract: Systems and methods are disclosed to provide an autonomous management of communication links between dice on a multi-die assembly. Each die can include a detection unit and a controller to detect a failing communication link and perform link maintenance by directing the communication traffic on the failing link to an operational link before the link fails. Once the failing link has been repaired, the controller can re-direct the traffic back to the repaired link. The controllers on each die can negotiate through a handshake process to provide the continuous operation by switching the communication traffic from the failing link to the operational link, and then from the operational link to the repaired link.

公开(公告)号：US11726665B1

公开(公告)日：2023-08-15

申请号：US17305044

申请日：2021-06-29

Applicant: Amazon Technologies, Inc.

Inventor： Erez Sabbag ,  Itai Avron

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0652 ,  G06F3/0655 ,  G06F3/0679

Abstract: Techniques for encoding additional data in a memory without requiring an increase to the physical storage capacity of the memory device are described. Additional data can be encoded with error correction code symbols without having to physically store the additional data in memory, while retaining the number of error correction code bits used by the memory. When data is read from memory without the additional data, erasure decoding can be performed to recover the additional data. When errors are encountered in the data read from memory, the errors can be treated as erasures for different predictions of the error locations to determine if the errors can be corrected.

公开(公告)号：US11182103B1

公开(公告)日：2021-11-23

申请号：US16261198

申请日：2019-01-29

Applicant: Amazon Technologies, Inc.

Inventor： Itai Avron ,  Adi Habusha ,  Uri Leder ,  Svetlana Kantorovych

IPC: G06F3/06 ,  G06F12/0806 ,  G06F12/0875 ,  G06F12/0873

Abstract: A dedicated input/output (I/O) cache can be used for I/O-to-processor communications. Data received from an I/O device can be written to the I/O cache and also written to a device memory that is accessible to the processor. The processor can then access the data in the fast, dedicated I/O cache if available. Otherwise, the processor can read the data from the memory into a conventional processor cache for processing. Writes to the cache can be full or partial, with partial writes utilizing padding in some embodiments. The data can be written sequentially in a circular manner. Data processed by the processor can be invalidated, and invalidated data can be overwritten on a subsequent write. Phase bits can also be used to indicate the pass during which various writes were performed.

公开(公告)号：US11042494B1

公开(公告)日：2021-06-22

申请号：US16014833

申请日：2018-06-21

Applicant: Amazon Technologies, inc.

Inventor： Ali Ghassan Saidi ,  Adi Habusha ,  Itai Avron ,  Tzachi Zidenberg ,  Ofer Naaman

IPC: G06F9/455 ,  G06F13/24 ,  G06F11/07

Abstract: An interposer circuit is used between an interrupt controller and a processor core to facilitate direct injection of a virtual interrupt into a guest executing on the processor core, even though the interrupt controller does not support the direct injection. The interposer circuit can convert a command received from the interrupt controller for a physical interrupt into another command for a virtual interrupt to make the processor core believe that the processor core has received a virtual interrupt even though the interrupt controller is not able to provide the virtual interrupt. The virtual interrupt can be directly injected into the processor core without the intervention of a hypervisor executing on the processor core.

公开(公告)号：US10824506B1

公开(公告)日：2020-11-03

申请号：US16215222

申请日：2018-12-10

Applicant: Amazon Technologies, Inc.

Inventor： Itai Avron ,  Adi Habusha

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

Abstract: A method and circuit are disclosed to calculate an error correction code (ECC) and perform a decompression in parallel when reading memory data. There are multiple modes of operation. In a normal parallel mode of operation, the data passes through a decompression engine. Simultaneously, the same data passes through an ECC decode engine. However, if no error is detected, the output of the decode engine is discarded. If there is an ECC error, an error indication is made so that the corresponding data exiting the decompression engine is discarded. The circuit then switches to a serial mode of operation, wherein the ECC decode engine corrects the data and resends the corrected data again through the decompression engine. The circuit is maintained in the serial mode until a decision is made to switch back to the parallel mode, such as when a pipeline of the ECC engine becomes empty.

公开(公告)号：US10067847B1

公开(公告)日：2018-09-04

申请号：US14848139

申请日：2015-09-08

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Itai Avron

IPC: G06F11/30 ,  G06F11/34

Abstract: Disclosed herein is a performance monitor for a functional block of a system, the performance monitor comprising a counter circuit, wherein the counter circuit includes a programmable time window counter configured to determine an adjustable counting period, and an event counter coupled to the time window counter. The event counter is configured to count a number of occurrences of an event occurring in the functional block during the counting period, and record the number of occurrences of the event during the counting period and generate an output trigger signal when the number of occurrences of the event during the counting period is outside of a programmable threshold band, or after receiving an input trigger signal from a cross trigger network triggered by other performance monitors in electrical communication with the cross trigger network.