公开(公告)号：US06813193B2

公开(公告)日：2004-11-02

申请号：US10406019

申请日：2003-04-02

申请人： Thomas Vogelsang

发明人： Thomas Vogelsang

IPC分类号： G11C700

CPC分类号： G11C7/106 ,  G11C7/1012 ,  G11C7/1051 ,  G11C11/4093 ,  G11C11/4096

摘要： A method of outputting data from a memory device, such as a dynamic random access memory, is disclosed. The method comprises the steps of providing an integrated circuit having a plurality of memory arrays; separately buffering data from separate memory arrays of the plurality of memory arrays; multiplexing buffered data from the separate memory arrays; and outputting the buffered data from the memory device. A circuit for employing the method is also disclosed.

摘要翻译： 公开了一种从诸如动态随机存取存储器的存储器件输出数据的方法。 该方法包括提供具有多个存储器阵列的集成电路的步骤; 分别从多个存储器阵列的独立存储器阵列缓冲数据; 从分离的存储器阵列复用缓冲数据; 并从存储器件输出缓冲的数据。 还公开了一种采用该方法的电路。

公开(公告)号：US5559353A

公开(公告)日：1996-09-24

申请号：US332737

申请日：1994-11-01

申请人： Lothar Risch ,  Thomas Vogelsang ,  Franz Hofmann ,  Karl Hofmann

发明人： Lothar Risch ,  Thomas Vogelsang ,  Franz Hofmann ,  Karl Hofmann

IPC分类号： H01L21/8238 ,  H01L21/762 ,  H01L27/092 ,  H03K19/0948 ,  H01L29/78

CPC分类号： H03K19/0948 ,  H01L21/76294 ,  H01L27/0922

摘要： A first MOS transistor and a second MOS transistor are connected in series with a first complementary MOS transistor and a second complementary MOS transistor that are connected in parallel with one another. The transistors are each realized as a vertical layer sequence that forms the source, channel and drain and that which has a sidewall at which a gate dielectric and a gate electrode are arranged. The complementary MOS transistors connected in parallel with one another are realized in a common layer sequence of the source, channel and drain. The layer sequences that form the series-connected transistors are arranged above one another. The circuit structure is manufactured by epitaxal definition of the layer sequences, such as by molecular beam epitaxy.

摘要翻译： 第一MOS晶体管和第二MOS晶体管与彼此并联连接的第一互补MOS晶体管和第二互补MOS晶体管串联连接。 晶体管各自被实现为形成源极，沟道和漏极的垂直层序列，并且其具有设置栅极电介质和栅电极的侧壁。 在源极，沟道和漏极的公共层序列中实现彼此并联连接的互补MOS晶体管。 形成串联晶体管的层序列彼此重叠。 电路结构通过层序列的上层定义（例如通过分子束外延）来制造。

公开(公告)号：US09361960B2

公开(公告)日：2016-06-07

申请号：US13394533

申请日：2010-08-23

申请人： Thomas Vogelsang

发明人： Thomas Vogelsang

IPC分类号： G06F12/00 ,  G11C8/12 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4096

CPC分类号： G11C8/12 ,  G11C7/1012 ,  G11C7/1045 ,  G11C11/4087 ,  G11C11/4096 ,  G11C2207/002 ,  G11C2207/105

摘要： A memory device has a storage array having a plurality of accessible memory banks and a configurable first set of memory segments. The plurality of accessible memory banks include a second set of memory segments. During a first mode of operation, the first set of memory segments is configured to be an additional accessible memory bank. During a second mode of operation, a pair of memory segments in the first set of memory segments are configured to be an additional set of memory segments in each of the plurality of accessible memory banks.

摘要翻译： 存储器件具有存储阵列，其具有多个可存取存储体和可配置的第一组存储器段。 多个可存储存储体包括第二组存储器段。 在第一操作模式期间，第一组存储器段被配置为附加的可访问存储体。 在第二操作模式期间，第一组存储器段中的一对存储器段被配置为在多个可存取存储体的每一个中的另外一组存储器段。

公开(公告)号：US09286965B2

公开(公告)日：2016-03-15

申请号：US13990363

申请日：2011-11-11

申请人： Richard Perego ,  Thomas Vogelsang ,  John Brooks

发明人： Richard Perego ,  Thomas Vogelsang ,  John Brooks

IPC分类号： G11C11/406

CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/408 ,  G11C2211/4061

摘要： The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.

摘要翻译： 本公开描述了DRAM架构和刷新控制器，其允许与指向DRAM设备的正常行激活命令同时调度DRAM设备的机会性刷新。 每个激活命令提供了在没有调度冲突的情况下刷新存储器设备内的另一独立行（即字线）的“机会”。

公开(公告)号：US09111588B2

公开(公告)日：2015-08-18

申请号：US13885225

申请日：2011-12-07

申请人： Thomas Vogelsang

发明人： Thomas Vogelsang

IPC分类号： G11C5/00 ,  G11C5/06 ,  G11C5/02 ,  G11C8/12

CPC分类号： G11C11/4093 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C8/12 ,  G11C11/4082

摘要： A memory die for use in a multi-die stack having at least one other die. The memory die includes a plurality of contacts arranged in a field and configured to interface to the other dies of the multi-die stack. A first subset of the buffer lines of a number of buffer lines are connected to respective contacts in the field. The memory die also includes a number of buffers and cross-bar lines. The buffers are coupled between respective signal lines and respective buffer lines. The cross-bar lines interconnect respective pairs of buffer lines in a second subset of the buffer lines that is distinct from the first subset of the buffer lines.

摘要翻译： 一种用于具有至少一个其它管芯的多管芯堆叠中的存储管芯。 存储器管芯包括布置在场中并被配置为与多管芯堆叠的其它管芯接合的多个触点。 多个缓冲线的缓冲线的第一子集连接到现场的各个触点。 存储器管芯还包括多个缓冲器和横条线。 缓冲器耦合在相应的信号线和相应的缓冲线之间。 跨条线将与缓冲线的第一子集不同的缓冲线的第二子集中的各对缓冲线相互连接。

公开(公告)号：US07797511B2

公开(公告)日：2010-09-14

申请号：US11650120

申请日：2007-01-05

申请人： Thomas Vogelsang

发明人： Thomas Vogelsang

IPC分类号： G06F12/00 ,  G06F21/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C11/40615

摘要： A memory device includes a memory array containing a plurality of memory addresses. An input terminal receives a requested one of the memory addresses and a memory controller is configured to refresh a first refresh address in response to a comparison of the received memory address and the first refresh address. In certain embodiments, the first refresh address is refreshed if it does not conflict with the received memory. If the first refresh address and the received memory address conflict, a second refresh address is refreshed. The received memory address is accessed simultaneously with the refresh in exemplary embodiments.

摘要翻译： 存储器件包括包含多个存储器地址的存储器阵列。 输入终端接收所请求的一个存储器地址，并且存储器控制器被配置为响应于所接收的存储器地址与第一刷新地址的比较来刷新第一刷新地址。 在某些实施例中，如果第一刷新地址与所接收的存储器不冲突，则刷新第一刷新地址。 如果第一个刷新地址和接收到的存储器地址冲突，则刷新第二个刷新地址。 在示例性实施例中，与刷新同时访问所接收的存储器地址。

公开(公告)号：US20080282001A1

公开(公告)日：2008-11-13

申请号：US11746946

申请日：2007-05-10

申请人： Thomas Vogelsang

发明人： Thomas Vogelsang

IPC分类号： G06F13/12

CPC分类号： G06F13/4217 ,  Y02D10/14 ,  Y02D10/151

摘要： A semiconductor device includes a first circuit block, a second circuit block, and a data bus. The data bus is coupled between the first and second circuit blocks. A first data inverter on the data bus inverts a selected segment of data that is transferred onto the data bus. A second data inverter at an end of the data bus re-inverts the selected segment of data before the data is transferred off the data bus. The data that is transferred onto the data is not analyzed in order to determine the selected segment of data that is inverted.

摘要翻译： 半导体器件包括第一电路块，第二电路块和数据总线。 数据总线耦合在第一和第二电路块之间。 数据总线上的第一个数据逆变器将转移到数据总线上的所选择的数据段进行反相。 数据总线末端的第二个数据反相器在数据从数据总线传输之前重新反转所选择的数据段。 不分析传输到数据上的数据，以便确定所选择的数据段被反转。

公开(公告)号：US07375999B2

公开(公告)日：2008-05-20

申请号：US11241592

申请日：2005-09-29

申请人： Thomas Vogelsang

发明人： Thomas Vogelsang

IPC分类号： G11C11/24 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C2211/4013

摘要： Embodiments of the invention provide a method and apparatus for accessing a twin cell memory device. In one embodiment, a twin memory cell is accessed using a first bitline and a second bitline. The method includes precharging the first bitline and the second bitline to a low voltage. A wordline voltage is asserted to access the twin memory cell. A voltage difference between the first and second bitline is created by a data value and a complement of the data value stored in the twin memory cell, and the voltage difference is sensed.

摘要翻译： 本发明的实施例提供一种用于访问双胞细胞存储器件的方法和装置。 在一个实施例中，使用第一位线和第二位线访问双存储器单元。 该方法包括将第一位线和第二位线预充电到低电压。 断言字线电压以访问双存储单元。 通过存储在双存储单元中的数据值和数据值的补码产生第一位线和第二位线之间的电压差，并且检测电压差。

公开(公告)号：US07342291B2

公开(公告)日：2008-03-11

申请号：US11402412

申请日：2006-04-12

申请人： Thomas Vogelsang

发明人： Thomas Vogelsang

IPC分类号： H01L29/00

CPC分类号： H03K19/0013 ,  H01L27/0925 ,  H01L27/0928 ,  Y10S257/901

摘要： An integrated circuit device including a plurality of MOSFETs of similar type and geometry is formed on a substrate with an ohmic contact, and an adjustable voltage source on the die utilizing clearable fuses is coupled between the ohmic contact and the sources of the MOSFETs. After die processing, a post-processing test is performed to measure an operating characteristic of the die such as leakage current or switching speed, and an external voltage source is applied and adjusted to control the operating characteristic. The on-die fuses are then cleared to adjust the on-die voltage source to match the externally applied voltage. The operating characteristic may be determined by including a test circuit on the die to exhibit the operating characteristic such as a ring oscillator frequency. This approach to controlling manufacturing-induced device performance variations is well suited to efficient manufacture of small feature-size circuits such as DRAMs.

摘要翻译： 在具有欧姆接触的衬底上形成包括具有相似类型和几何形状的多个MOSFET的集成电路器件，并且使用可清除熔丝的管芯上的可调电压源耦合在欧姆接触和MOSFET的源极之间。 在模具处理之后，进行后处理试验以测量管芯的工作特性，例如漏电流或开关速度，施加外部电压源并进行调整以控制工作特性。 然后清除管芯内保险丝以调整片上电压源以匹配外部施加的电压。 操作特性可以通过在芯片上包括测试电路来表现出诸如环形振荡器频率的工作特性来确定。 用于控制制造引起的器件性能变化的这种方法非常适合于诸如DRAM的小型特征尺寸电路的有效制造。

公开(公告)号：US20060140040A1

公开(公告)日：2006-06-29

申请号：US11025561

申请日：2004-12-29

申请人： Thomas Vogelsang ,  Harald Lorenz ,  Wolfgang Hokenmaier

发明人： Thomas Vogelsang ,  Harald Lorenz ,  Wolfgang Hokenmaier

IPC分类号： G11C8/00 ,  G11C8/10

CPC分类号： G11C8/10 ,  G11C11/405 ,  G11C11/4087 ,  G11C2211/4013

摘要： A memory circuit comprises a memory including a memory array, a twin cell mode predecoder, and a row address predecoder. The memory array comprises word lines. The twin cell mode predecoder is configured for selecting one of four word line activation configurations for the memory array. The four word line activation configurations include three twin cell word line activation configurations and a single cell word line activation configuration. The row address predecoder is configured for selecting one of four word lines if the single cell word line activation configuration is selected.

摘要翻译： 存储器电路包括存储器，其包括存储器阵列，双单元模式预解码器和行地址预解码器。 存储器阵列包括字线。 双胞胎模式预解码器被配置用于选择存储器阵列的四个字线激活配置之一。 四个字线激活配置包括三个双胞胎字线激活配置和单个单元格字线激活配置。 行地址预解码器被配置为如果选择了单个单元字线激活配置，则选择四个字线之一。