公开(公告)号：US20090195258A1

公开(公告)日：2009-08-06

申请号：US12026143

申请日：2008-02-05

申请人： Andreas Jakobs

发明人： Andreas Jakobs

IPC分类号： G01R35/00

CPC分类号： G11C5/063 ,  G11C7/1066 ,  G11C2207/2254

摘要： A method of controlling an analog signal in an integrated circuit includes generating a first control signal having a first predetermined duration within the integrated circuit. The first control signal is configured to cause the analog signal to have a first signal level. The first signal level is compared to a level of a target signal. A second control signal is generated within the integrated circuit based on a result of the comparison. The second control signal is configured to cause the analog signal to have a second signal level. The second control signal has a second predetermined duration that is different than the first predetermined duration.

摘要翻译： 一种在集成电路中控制模拟信号的方法包括：在集成电路内产生具有第一预定持续时间的第一控制信号。 第一控制信号被配置为使得模拟信号具有第一信号电平。 将第一信号电平与目标信号的电平进行比较。 基于比较的结果，在集成电路内产生第二控制信号。 第二控制信号被配置为使得模拟信号具有第二信号电平。 第二控制信号具有与第一预定持续时间不同的第二预定持续时间。

公开(公告)号：US07339407B2

公开(公告)日：2008-03-04

申请号：US11360988

申请日：2006-02-23

申请人： Andreas Jakobs ,  Torsten Hinz ,  Benaissa Zaryouh

发明人： Andreas Jakobs ,  Torsten Hinz ,  Benaissa Zaryouh

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03K5/133 ,  H03K2005/00026 ,  H03L7/0814 ,  H03L7/087

摘要： The invention relates to a DLL circuit for providing an adjustable time delay of a periodic input signal, said circuit having controllable delay elements which are connected in series and form a delay chain, having a phase detector in order to generate a control signal on the basis of the periodic input signal and a periodic signal which has been delayed by the delay chain, the delay of each of the delay elements being adjusted on the basis of the control signal, and having a selection unit which is respectively connected to one of the delay elements in order to apply an output signal from one of the delay elements to an output of the DLL circuit on the basis of a selection variable which has been provided, and a compensation circuit which modifies the selection signal such that an additional delay (which is caused at least by the selection unit) between the periodic input signal and the output signal from the DLL circuit is compensated for.

摘要翻译： 本发明涉及一种用于提供周期性输入信号的可调时间延迟的DLL电路，所述电路具有可串联连接并形成延迟链的可控延迟元件，具有相位检测器，以便在此基础上产生控制信号 和延迟链延迟的周期信号，基于控制信号调整每个延迟元件的延迟，并且具有选择单元，其分别连接到延迟链中的一个延迟 元件，以便根据所提供的选择变量将来自延迟元件之一的输出信号施加到DLL电路的输出;以及补偿电路，其修改选择信号，使得附加延迟（即 至少由选择单元引起的）周期性输入信号与来自DLL电路的输出信号进行补偿。

公开(公告)号：US07061784B2

公开(公告)日：2006-06-13

申请号：US10886814

申请日：2004-07-08

申请人： Andreas Jakobs ,  Hermann Ruckerbauer ,  Maksim Kuzmenka

发明人： Andreas Jakobs ,  Hermann Ruckerbauer ,  Maksim Kuzmenka

IPC分类号： G11C5/06

CPC分类号： G11C11/4093 ,  G11C5/063 ,  G11C7/10

摘要： The invention relates to a semiconductor memory module having at least one memory chip and a buffer chip, which drives clock, address and command signals to the memory chip and drives data signals to, and receives them from, the memory chip via a module-internal clock, address, command and data bus. The buffer chip forms an interface to an external memory main bus. The data bus lines and/or the clock, command and address bus lines are respectively connected to the buffer chip at their two ends and are capable of being driven by the buffer chip from these two ends. Control means are being provided and set up in such a manner that they respectively match the directions of propagation of the data signals and of the clock, command and address signals on the corresponding bus lines during writing and reading.

摘要翻译： 本发明涉及一种具有至少一个存储器芯片和缓冲芯片的半导体存储器模块，其将时钟，地址和命令信号驱动到存储器芯片，并且经由模块内部驱动数据信号并从存储器芯片接收它们 时钟，地址，命令和数据总线。 缓冲芯片形成与外部存储器主总线的接口。 数据总线和/或时钟，命令和地址总线分别在两端分别连接到缓冲芯片，并且能够被这两端的缓冲芯片驱动。 正在提供和设置控制装置，使得它们在写入和读取期间它们分别匹配数据信号的传播方向以及相应总线上的时钟，命令和地址信号。

公开(公告)号：US07016259B2

公开(公告)日：2006-03-21

申请号：US10949793

申请日：2004-09-24

申请人： Andreas Jakobs

发明人： Andreas Jakobs

IPC分类号： G11C8/18

CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2254

摘要： A calibration apparatus is provided for adjusting the relative phase between two signals received at a memory chip, the two signals being generated such that they are synchronized with one another in a controller and are transmitted to the memory chip via separate lines. The calibration apparatus comprises a measuring device, which is arranged in the memory chip and is designed for measuring the relative phase between the two received signals, and a feedback loop containing a phase-controlling correction device. The measuring device is designed for generating an item of control information indicating the deviation of the measured relative phase from a defined tolerance range. The correction device responds to the control information to compensate for the deviation. The correction device is arranged in the controller and is designed for influencing the relative phase between the two signals to be transmitted to the memory chip. The feedback loop contains a signal connection leading from the memory chip to the controller.

摘要翻译： 提供了一种校准装置，用于调整在存储器芯片处接收的两个信号之间的相对相位，这两个信号被产生，使得它们在控制器中彼此同步，并通过分离的线路传送到存储器芯片。 校准装置包括测量装置，其被布置在存储器芯片中并且被设计用于测量两个接收信号之间的相对相位，以及包括相位控制校正装置的反馈回路。 测量装置被设计用于产生指示所测量的相对相位与限定的公差范围的偏差的控制信息项。 校正装置响应控制信息以补偿偏差。 校正装置被布置在控制器中，并且被设计用于影响要发送到存储芯片的两个信号之间的相对相位。 反馈回路包含从存储芯片引导到控制器的信号连接。

公开(公告)号：US20090298457A1

公开(公告)日：2009-12-03

申请号：US12131276

申请日：2008-06-02

申请人： Andreas Jakobs

发明人： Andreas Jakobs

IPC分类号： H04B1/16

CPC分类号： H03F3/3022 ,  H03F1/56 ,  H03F3/72 ,  H03F2200/456 ,  H03F2200/78 ,  H03F2203/7236 ,  H04L25/0278

摘要： A method of calibrating an output driver circuit includes providing a comparator to compare drive signals to a reference signal. The reference signal is adjusted to compensate an offset voltage of the comparator. A first drive signal is compared to the adjusted reference signal by the comparator. The first drive signal is adjusted to match the adjusted reference signal, thereby calibrating a first impedance of the output driver circuit.

摘要翻译： 校准输出驱动器电路的方法包括提供比较器以将驱动信号与参考信号进行比较。 调整参考信号以补偿比较器的偏移电压。 比较器将第一驱动信号与调整的参考信号进行比较。 调整第一驱动信号以匹配调整的参考信号，从而校准输出驱动器电路的第一阻抗。

公开(公告)号：US07518935B2

公开(公告)日：2009-04-14

申请号：US11390557

申请日：2006-03-27

申请人： Andreas Jakobs

发明人： Andreas Jakobs

IPC分类号： G11C7/10 ,  G11C7/22

CPC分类号： G11C7/1093 ,  G06F13/1689 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/4093

摘要： One embodiment of the invention relates to a RAM memory circuit. A memory circuit includes a multiplicity of memory cells which can be selectively addressed, I/O circuitry for data; a clock input for receiving a system clock signal; a reception sampling circuit for sampling the received data using a reception strobe signal; and a reception strobe signal generating device which internally generates the reception strobe signal with synchronization with the received system clock signal.

摘要翻译： 本发明的一个实施例涉及RAM存储器电路。 存储器电路包括可以选择性寻址的多个存储器单元，用于数据的I / O电路; 用于接收系统时钟信号的时钟输入; 接收采样电路，用于使用接收选通信号对接收到的数据进行采样; 以及与所接收的系统时钟信号同步地在内部产生接收选通信号的接收选通信号发生装置。

公开(公告)号：US07456665B2

公开(公告)日：2008-11-25

申请号：US11464999

申请日：2006-08-16

申请人： Torsten Hinz ,  Andreas Jakobs ,  Benaissa Zaryouh

发明人： Torsten Hinz ,  Andreas Jakobs ,  Benaissa Zaryouh

IPC分类号： H03L7/06

CPC分类号： H03K5/135 ,  H03K5/133 ,  H03K2005/00032 ,  H03K2005/00058 ,  H03K2005/00156 ,  H03L7/0805 ,  H03L7/0814

摘要： A Phase shifter for generating a phase-shifted, in particular phase-delayed, output signal from an input signal is disclosed. In one embodiment, the phase shifter includes a first delay line and at least one further delay line with respectively cascaded delay elements that form a U-shaped signal path along which at least one delay element is adapted to be controlled to be optionally opening or closing. A phase discriminator located at the input side of which a clock signal and a signal from one of the delay lines can be applied, and the output side of which is connected with a respective control input of the delay elements. The clock signal can also be applied to the first delay line, so that a feedback loop is formed by the phase discriminator and at least one of the delay lines. The input signal can be applied to the delay line whose signal output is not connected with the phase discriminator, and the output signal can be output therefrom.

摘要翻译： 公开了一种用于从输入信号产生相移的，特别是相位延迟的输出信号的移相器。 在一个实施例中，移相器包括第一延迟线和至少一个另外的延迟线，其具有分别级联的延迟元件，其形成U形信号路径，至少一个延迟元件沿着该延伸元件被控制为可选地打开或关闭 。 位于其输入侧的相位鉴别器可以施加来自延迟线之一的时钟信号和信号，其输出侧与延迟元件的相应控制输入相连。 时钟信号也可以被施加到第一延迟线，使得由相位鉴别器和至少一个延迟线形成反馈回路。 输入信号可以施加到信号输出不与鉴相器连接的延迟线，并且可以从其输出输出信号。

公开(公告)号：US07386696B2

公开(公告)日：2008-06-10

申请号：US10887019

申请日：2004-07-08

申请人： Andreas Jakobs ,  Hermann Ruckerbauer ,  Maksim Kuzmenka

发明人： Andreas Jakobs ,  Hermann Ruckerbauer ,  Maksim Kuzmenka

IPC分类号： G06F12/00

CPC分类号： G11C5/063

摘要： The invention relates to a semiconductor memory module having a plurality of memory chips arranged in at least one row and at least one buffer chip which drives and receives clock signals and command and address signals to the memory chips and data signals to and from the memory chips via a clock, address, command and data bus inside the module and which forms an interface to an external primary memory bus. The semiconductor memory module has an even number of buffer chips arranged on it and all of the memory chips are connected to two respective buffer chips at least by one signal line type from a signal group and just to one of the two buffer chips by the remaining signal lines from the group. The sum of the electrical signal propagation times for the actuating signals via their lines from one buffer chip to a respective one of the memory chips and the electrical signal propagation times for the data signals from this memory chip to the other buffer chip during the read operation is the same for all of the memory chips, and control means for controlling the respective data write and read operation to or from the memory chips are provided in order to drive the clock signals and command and address signals in the same respective direction as the data signals via the bus inside the module when data are being written and read.

摘要翻译： 本发明涉及一种半导体存储器模块，其具有布置在至少一行的多个存储器芯片和至少一个缓冲器芯片，该缓冲器芯片驱动并接收时钟信号，以及将命令和寻址信号存储到存储器芯片以及从存储器芯片传送数据信号 通过模块内的时钟，地址，命令和数据总线，并形成与外部主存储器总线的接口。 半导体存储器模块具有布置在其上的偶数个缓冲器芯片，并且所有存储器芯片至少通过一个信号线类型从信号组连接到两个相应的缓冲器芯片，并且仅剩下两个缓冲器芯片之一 来自该组的信号线。 在读取操作期间，通过其线从一个缓冲芯片到相应的一个存储器芯片的致动信号的电信号传播时间和从该存储器芯片到另一个缓冲器芯片的数据信号的电信号传播时间之和 对于所有存储器芯片是相同的，并且提供用于控制到存储器芯片或从存储器芯片的相应数据写入和读取操作的控制装置，以便以与数据相同的相同方向驱动时钟信号和命令和寻址信号 当数据被写入和读取时通过模块内的总线发送信号。

公开(公告)号：US07224636B2

公开(公告)日：2007-05-29

申请号：US10890934

申请日：2004-07-14

申请人： Andreas Jakobs ,  Hermann Ruckerbauer ,  Maksim Kuzmenka

发明人： Andreas Jakobs ,  Hermann Ruckerbauer ,  Maksim Kuzmenka

IPC分类号： G11C8/00

CPC分类号： G11C29/028 ,  G11C5/063 ,  G11C29/50012

摘要： The invention relates to a semiconductor memory module having a plurality of memory chips arranged next to one another in a row. The memory module has a module-internal clock, command/address and data bus which transfers clock signal, command and address signals and also data signals from a memory controller device to the memory chips and data signals from the memory chips to the memory controller device. The memory module has respective clock, command/address and data signal lines. The clock signal lines comprise two differential clock signal lines which, at their end opposite to the memory controller device are either open or connected to one another by a short-circuiting bridge. The memory chips, during a write operation, synchronize the write data with the clock signal running from the memory controller device to the end of the clock signal line and, during a read operation, output the read data synchronously with the clock signal reflected from the open or short-circuited end of the clock signal lines.

摘要翻译： 本发明涉及一种半导体存储器模块，该半导体存储器模块具有彼此排成一列的多个存储器芯片。 存储器模块具有模块内部时钟，命令/地址和数据总线，其将时钟信号，命令和地址信号以及数据信号从存储器控制器设备传送到存储器芯片，并将数据信号从存储器芯片传送到存储器控制器设备 。 存储器模块具有各自的时钟，命令/地址和数据信号线。 时钟信号线包括两个差分时钟信号线，它们在其与存储器控制器装置相对的端部通过短路桥断开或彼此连接。 在写入操作期间，存储器芯片将写入数据与从存储器控制器设备运行到时钟信号线的时钟信号同步，并且在读取操作期间，与从该存储器控制器设备反射的时钟信号同步地输出读取数据 开路或短路的时钟信号线。

公开(公告)号：US20060233031A1

公开(公告)日：2006-10-19

申请号：US11390557

申请日：2006-03-28

申请人： Andreas Jakobs

发明人： Andreas Jakobs

IPC分类号： G11C7/00

CPC分类号： G11C7/1093 ,  G06F13/1689 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/4093

摘要： One embodiment of the invention relates to a RAM memory circuit. A memory circuit includes a multiplicity of memory cells which can be selectively addressed, I/O circuitry for data; a clock input for receiving a system clock signal; a reception sampling circuit for sampling the received data using a reception strobe signal; and a reception strobe signal generating device which internally generates the reception strobe signal with synchronization with the received system clock signal.