公开(公告)号：US12229561B1

公开(公告)日：2025-02-18

申请号：US17933037

申请日：2022-09-16

Applicant: Apple Inc.

Inventor： Madhu Sudan Hari ,  Mridul Agarwal ,  Kulin N Kothari ,  John D Pape ,  Niket K Choudhary

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52 ,  G06F12/1027

Abstract: A system may include multiple processors. One of the processors may receive an indication of a data synchronization barrier (DSB) instruction in another processor that follows a translation look-ahead buffer invalidate (TLBI) instruction to invalidate an entry of a translation look-ahead buffer. The processor may determine whether instructions are pending in the processor for which the virtual addresses used for memory accesses have been translated to physical addresses before receiving the DSB indication. If there are such pending instructions, the processor may provide, after these instructions retire, an indication to the other processor as a response to the DSB indication.

公开(公告)号：US20240329990A1

公开(公告)日：2024-10-03

申请号：US18740430

申请日：2024-06-11

Applicant: Apple Inc.

Inventor： Deepankar Duggal ,  Kulin N Kothari ,  Mridul Agarwal ,  Chang Xu ,  Yanran Yang ,  Richard F Russo ,  Yuan C Chou ,  Douglas C Holman

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52

CPC classification number: G06F9/30087 ,  G06F9/3802 ,  G06F9/522

Abstract: A system, e.g., a system on a chip (SOC), may include one or more processors. A processor may execute an instruction synchronization barrier (ISB) instruction to enforce an ordering constraint on instructions. To execute the ISB instruction, the processor may determine whether contexts of the processor required for execution of instructions older than the ISB instruction are consumed for the older instructions. Responsive to determining that the contexts are consumed for the older instructions, the processor may initiate fetching of an instruction younger than the ISB instruction, without waiting for the older instructions to retire.

公开(公告)号：US20240311319A1

公开(公告)日：2024-09-19

申请号：US18674203

申请日：2024-05-24

Applicant: Apple Inc.

Inventor： Jeffrey E. Gonion ,  Charles E. Tucker ,  Tal Kuzi ,  Richard F. Russo ,  Mridul Agarwal ,  Christopher M. Tsay ,  Gideon N. Levinsky ,  Shih-Chieh Wen ,  Lior Zimet

IPC: G06F13/24 ,  G06F1/26

CPC classification number: G06F13/24 ,  G06F1/26

Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.

公开(公告)号：US20220083338A1

公开(公告)日：2022-03-17

申请号：US17469504

申请日：2021-09-08

Applicant: Apple Inc.

Inventor： Jeff Gonion ,  John H. Kelm ,  James Vash ,  Pradeep Kanapathipillai ,  Mridul Agarwal ,  Gideon N. Levinsky ,  Richard F. Russo ,  Christopher M. Tsay

IPC: G06F9/30 ,  G06F12/0875 ,  G06F12/02

Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.

公开(公告)号：US10228951B1

公开(公告)日：2019-03-12

申请号：US14831661

申请日：2015-08-20

Applicant: Apple Inc.

Inventor： Kulin N. Kothari ,  Mridul Agarwal ,  Pradeep Kanapathipillai

IPC: G06F9/38 ,  G06F9/30

Abstract: Systems, apparatuses, and methods for committing store instructions out of order from a store queue are described. A processor may store a first store instruction and a second store instruction in the store queue, wherein the first store instruction is older than the second store instruction. In response to determining the second store instruction is ready to commit to the memory hierarchy, the processor may allow the second store instruction to commit before the first store instruction, in response to determining that all store instructions in the store queue older than the second store instruction are non-speculative. However, if it is determined that at least one store instruction in the store queue older than the second store instruction is speculative, the processor may prevent the second store instruction from committing to the memory hierarchy before the first store instruction.

公开(公告)号：US20240362027A1

公开(公告)日：2024-10-31

申请号：US18764611

申请日：2024-07-05

Applicant: Apple Inc.

Inventor： Yuan C. Chou ,  Debasish Chandra ,  Mridul Agarwal ,  Haoyan Jia

IPC: G06F9/38

CPC classification number: G06F9/3842 ,  G06F9/383 ,  G06F9/3832

Abstract: Techniques are disclosed relating to load value prediction. In some embodiments, a processor includes load address prediction circuitry and load value prediction circuitry. Training circuitry may train loads in a given entry, and may include a first entry configured to store first predicted load address information and a confidence indication of confidence that the first predicted load address information is correct and a second entry configured to store first predicted load value information and a confidence indication of confidence that the first predicted load value information is correct (note a given entry may be configured to load or value prediction at different times). Control circuitry may, in response to an entry in the training circuitry reaching a threshold level of confidence, allocate a corresponding entry in either the load value prediction circuitry or the load address prediction circuitry.

公开(公告)号：US12045615B1

公开(公告)日：2024-07-23

申请号：US17933040

申请日：2022-09-16

Applicant: Apple Inc.

Inventor： Deepankar Duggal ,  Kulin N Kothari ,  Mridul Agarwal ,  Chang Xu ,  Yanran Yang ,  Richard F Russo ,  Yuan C Chou ,  Douglas C Holman

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52

CPC classification number: G06F9/30087 ,  G06F9/3802 ,  G06F9/522

Abstract: A system, e.g., a system on a chip (SOC), may include one or more processors. A processor may execute an instruction synchronization barrier (ISB) instruction to enforce an ordering constraint on instructions. To execute the ISB instruction, the processor may determine whether contexts of the processor required for execution of instructions older than the ISB instruction are consumed for the older instructions. Responsive to determining that the contexts are consumed for the older instructions, the processor may initiate fetching of an instruction younger than the ISB instruction, without waiting for the older instructions to retire.

公开(公告)号：US11829763B2

公开(公告)日：2023-11-28

申请号：US16539684

申请日：2019-08-13

Applicant: Apple Inc.

Inventor： Yuan C. Chou ,  Viney Gautam ,  Wei-Han Lien ,  Kulin N. Kothari ,  Mridul Agarwal

IPC: G06F9/345 ,  G06F9/38 ,  G06F9/30 ,  G06F9/50 ,  G06F12/0802

CPC classification number: G06F9/3455 ,  G06F9/30043 ,  G06F9/3861 ,  G06F9/5005 ,  G06F12/0802

Abstract: A system and method for efficiently reducing the latency of load operations. In various embodiments, logic of a processor accesses a prediction table after fetching instructions. For a prediction table hit, the logic executes a load instruction with a retrieved predicted address from the prediction table. For a prediction table miss, when the logic determines the address of the load instruction and hits in a learning table, the logic updates a level of confidence indication to indicate a higher level of confidence when a stored address matches the determined address. When the logic determines the level of confidence indication stored in a given table entry of the learning table meets a threshold, the logic allocates, in the prediction table, information stored in the given entry. Therefore, the predicted address is available during the next lookup of the prediction table.

公开(公告)号：US11500638B1

公开(公告)日：2022-11-15

申请号：US16739464

申请日：2020-01-10

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  James Vash ,  Pradeep Kanapathipillai ,  Mridul Agarwal ,  Zhaoming Hu ,  Tyler Huberty ,  Charles Tucker

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875

Abstract: A method and system for compressing and decompressing data is disclosed. A compression command may initiate the prefetching of first data, which may be stored in a first buffer. Multiple words of the first data may be read from the first buffer and used to generate a plurality of compressed packets, each of which includes a command specifying a type of packet. The compressed packets may be combined into a group and multiple groups may be combined and stored in a second buffer. A decompression command may initiate the prefetching of second data, which is stored in the first buffer. A portion of the second data may be read from the first buffer and used to generate a group of compressed packets. Multiple output words may be generated dependent upon the group of compressed packets.

公开(公告)号：US20220083484A1

公开(公告)日：2022-03-17

申请号：US17246311

申请日：2021-04-30

Applicant: Apple Inc.

Inventor： Jeffrey E. Gonion ,  Charles E. Tucker ,  Tal Kuzi ,  Richard F. Russo ,  Mridul Agarwal ,  Christopher M. Tsay ,  Gideon N. Levinsky ,  Shih-Chieh Wen

IPC: G06F13/24 ,  G06F1/26

Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.