-
公开(公告)号：US11681636B2
公开(公告)日：2023-06-20
申请号：US16981816
申请日：2019-02-12
Applicant: Arm Limited
Inventor： Graeme Peter Barnes , Jasen Milov Borisov
IPC: G06F12/14 , G06F7/58 , G06F9/30 , G06F21/79 , G06F12/0842 , G06F12/0853 , G06F12/0897 , G06F12/1027
CPC classification number: G06F12/1441 , G06F7/582 , G06F9/3004 , G06F9/30076 , G06F9/30101 , G06F9/30145 , G06F12/0842 , G06F12/0853 , G06F12/0897 , G06F12/1027 , G06F21/79
Abstract: An apparatus has processing circuitry (4); memory access circuitry (15) to perform a guard tag check for a tag checking target address having an associated address tag, the guard tag check comprising comparing the address tag with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address; and an instruction decoder (6) responsive to a random tag setting instruction specifying a tag setting target address, to control the processing circuitry (4) to set the address tag associated with the tag setting target address to a random tag value randomly selected from a set of candidate tag values.
-
公开(公告)号：US11481384B2
公开(公告)日：2022-10-25
申请号：US16094224
申请日：2017-03-29
Applicant: ARM LIMITED
Inventor： Graeme Peter Barnes , Stuart David Biles
Abstract: An apparatus is provided comprising storage elements to store data blocks, where each data block has capability metadata associated therewith identifying whether the data block specifies a capability, at least one capability type being a bounded pointer. Processing circuitry is then arranged to be responsive to a bulk capability metadata operation identifying a plurality of the storage elements, to perform an operation on the capability metadata associated with each data block stored in the plurality of storage elements. Via a single specified operation, this hence enables query and/or modification operations to be performed on multiple items of capability metadata, hence providing more efficient access to such capability metadata.
-
公开(公告)号：US11080058B2
公开(公告)日：2021-08-03
申请号：US16619192
申请日：2018-04-27
Applicant: ARM LIMITED
Inventor： Graeme Peter Barnes
Abstract: An apparatus and method are provided for controlling a change in instruction set. The apparatus has processing circuitry arranged to operate in a capability domain comprising capabilities used to constrain operations performed by the processing circuitry. A program counter capability storage element is used to store a program counter capability used by the processing circuitry to determined a program counter value. The processing circuitry is arranged to employ a capability based operation to change the instruction set. In response to execution of at least one type of instruction to load an identified capability into the program counter capability storage element, the processing circuitry is arranged to invoke the capability based operation in order to perform a capability check operation in respect of the identified capability, and to cause the instruction set to be identified by an instruction set identifier field from the identified capability provided the capability check operation is passed.
-
公开(公告)号：US10650136B2
公开(公告)日：2020-05-12
申请号：US15770560
申请日：2016-09-30
Applicant: ARM LIMITED
Inventor： Graeme Peter Barnes
Abstract: An apparatus and method are provided for controlling use of bounded pointers. The apparatus has a plurality of bounded pointer storage elements, each bounded pointer storage element being used to store a bounded pointer and associated permission attributes indicative of allowed uses of the bounded pointer. In accordance with the present technique, the associated permission attributes include a copy permission attribute indicating whether the bounded pointer is allowed to be subjected to a copy operation. Processing circuitry is then responsive to at least one instruction that specifies the copy operation, to generate, from a source bounded pointer and associated permission attributes of a source bounded pointer storage element, a destination bounded pointer and associated permission attributes to be stored in a destination bounded pointer storage element. Furthermore, the processing circuitry marks the source bounded pointer storage element as storing an invalid bounded pointer dependent on whether the copy permission attribute of the source bounded pointer indicates that the source bounded pointer is to be prevented from being subjected to the copy operation. This provides an effective mechanism for inhibiting the subversion of control flow integrity when executing software on the apparatus.
-
公开(公告)号：US11762566B2
公开(公告)日：2023-09-19
申请号：US17370291
申请日：2021-07-08
Applicant: Arm Limited
Inventor： Richard Roy Grisenthwaite , Graeme Peter Barnes
IPC: G06F3/06
CPC classification number: G06F3/0622 , G06F3/0655 , G06F3/0673
Abstract: An apparatus comprises processing circuitry to perform data processing in response to instructions, and memory access circuitry to perform a tag-guarded memory access operation in response to a target address. The tag-guarded memory access operation comprises comparing an address tag associated with the target address with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address, and generating an indication of whether a match is detected between the guard tag and the address tag. The memory access circuitry determines, according to a programmable mapping, a mapping of guard tag storage locations for storing guard tags for corresponding blocks of memory locations.
-
Patent Agency Ranking
公开(公告)号：US11687464B2
公开(公告)日：2023-06-27
申请号：US16648041
申请日：2019-01-23
Applicant: ARM LIMITED
Inventor： Graeme Peter Barnes , Catalin Theodor Marinas , William James Deacon
IPC: G06F12/10
CPC classification number: G06F12/10 , G06F2212/657
Abstract: An apparatus comprises address translation circuitry (70) to perform a translation of a virtual address (80) comprising a virtual tag portion (88) and a virtual address portion (86) into a physical address (82) comprising a physical tag portion (92) and a physical address portion (90). The address translation circuitry comprises address tag translation circuitry (72) to perform a translation of the virtual tag portion into the physical tag portion and the address translation to be performed is selected in dependence on the virtual address.
-
公开(公告)号：US11347508B2
公开(公告)日：2022-05-31
申请号：US16607462
申请日：2018-04-27
Applicant: ARM LIMITED
Inventor： Graeme Peter Barnes
Abstract: An apparatus and method are provided for managing a capability domain. The apparatus has processing circuitry for executing instructions, the processing circuitry when in a default state being arranged to operate in a capability domain comprising capabilities used to constrain operations performed by the processing circuitry when executing the instructions. A program counter capability storage element is also provided to store a program counter capability used by the processing circuitry to determine a program counter value. The program counter capability is arranged to identify a capability state for the processing circuitry. The processing circuitry is then arranged, when the capability state indicates the default state, to operate in the capability domain. However, when the capability state indicates the executive state, the processing circuitry is arranged to operate in a manner less constrained than when in the default state so as to allow modification of the capability domain. This provides a simple and effective mechanism for selectively allowing the apparatus to modify the capability domain.
-
公开(公告)号：US11182294B2
公开(公告)日：2021-11-23
申请号：US16334095
申请日：2017-08-18
Applicant: ARM LIMITED
Inventor： Jason Parker , Graeme Peter Barnes
IPC: G06F12/10 , G06F12/0815 , G06F12/14
Abstract: A data processing apparatus 2 includes a cache memory 8 for storing data items to be accessed. Coherency control circuitry 20 controls coherency between data items stored within the cache memory and one or more other copies of the data items stored outside the cache memory. A data access buffer 6 buffers a plurality of data access to respective data items stored within the cache memory. Access control circuitry 20 is responsive to coherency statuses managed by the coherency control circuitry for the plurality of data items to be subject to data access operations to be performed together atomically as an atomic set of data accesses to ensure that the coherency statuses for all of these data items permit all of the atomic set of data accesses to be performed within the cache memory before the set of atomic data accesses are commenced.
-
公开(公告)号：US11119778B2
公开(公告)日：2021-09-14
申请号：US16620987
申请日：2018-06-20
Applicant: ARM LIMITED
Inventor： Graeme Peter Barnes
Abstract: An apparatus has processing circuitry to execute a sequence of instructions, an integer storage element to store an integer value for access by the processing circuitry, and a capability storage element for storing a capability for access by the processing circuitry. A capability usage storage is then used to store capability usage information. The processing circuitry is responsive to execution of at least one instruction in the sequence of instructions to generate, in dependence on the capability usage information, a result to be stored in a destination storage element, when the capability usage information identifies a capability state, the result is generated as a capability, and the capability storage element is selected as the destination storage element, and when the capability usage information identifies a non-capability state, the result is generated as an integer value, and the integer storage element is selected as the destination storage element.
-
公开(公告)号：US11023237B2
公开(公告)日：2021-06-01
申请号：US16607461
申请日：2018-04-27
Applicant: ARM LIMITED
Inventor： Graeme Peter Barnes
Abstract: An apparatus and method are provided for interpreting permissions associated with a capability. The apparatus has processing circuitry for executing instructions in order to perform operations, and a capability storage element accessible to the processing circuitry and arranged to store a capability used to constrain at least one operation performed by the processing circuitry when executing the instructions. The capability identifies a plurality N of default permissions whose state, in accordance with a default interpretation, is determined from N permission flags provided in the capability. In accordance with the default interpretation, each permission flag is associated with one of the default permissions. The processing circuitry is then arranged to analyse the capability in accordance with an alternative interpretation, in order to derive, from logical combinations of the N permission flags, state for an enlarged set of permissions, where the enlarged set comprises at least N+1 permissions. This provides a mechanism for encoding additional permissions into capabilities without increasing the number of permission flags required, whilst still retaining desirable behaviour.
-
-
-
-
-
-
-
-
-
Search Results
22
records
(took 0.018 seconds)
