公开(公告)号：US20060273413A1

公开(公告)日：2006-12-07

申请号：US11185678

申请日：2005-07-21

申请人： Motoyuki Sato ,  Katsuyuki Sekine ,  Kazuaki Nakajima ,  Tomohiro Saito ,  Kazuhiro Eguchi ,  Atsushi Yagishita

发明人： Motoyuki Sato ,  Katsuyuki Sekine ,  Kazuaki Nakajima ,  Tomohiro Saito ,  Kazuhiro Eguchi ,  Atsushi Yagishita

IPC分类号： H01L29/94

CPC分类号： H01L21/823462 ,  H01L21/82345 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： There are provided: a semiconductor substrate including first and second device regions isolated by device isolation regions; a first gate insulating film of a high-k material formed in the first device region; a first gate electrode formed on the first gate insulating film; first source and drain regions formed at both sides of the first gate electrode in the first device region; a second gate insulating film of a high-k material which is different from the high-k material of the first gate insulating film, the second gate insulating film being formed in the second device region; a second gate electrode formed on the second gate insulating film; and second source and drain regions formed at both sides of the second gate electrode in the second device region.

摘要翻译： 提供：包括由器件隔离区域隔离的第一和第二器件区域的半导体衬底; 形成在所述第一器件区域中的高k材料的第一栅极绝缘膜; 形成在第一栅极绝缘膜上的第一栅电极; 形成在第一器件区域中的第一栅电极的两侧的第一源极和漏极区; 与所述第一栅极绝缘膜的高k材料不同的高k材料的第二栅极绝缘膜，所述第二栅极绝缘膜形成在所述第二器件区域中; 形成在所述第二栅极绝缘膜上的第二栅电极; 以及形成在第二器件区域中的第二栅电极的两侧的第二源极和漏极区。

公开(公告)号：US06664592B2

公开(公告)日：2003-12-16

申请号：US10330280

申请日：2002-12-30

申请人： Seiji Inumiya ,  Tomohiro Saito ,  Atsushi Yagishita ,  Katsuhiko Hieda ,  Toshihiko Iinuma

发明人： Seiji Inumiya ,  Tomohiro Saito ,  Atsushi Yagishita ,  Katsuhiko Hieda ,  Toshihiko Iinuma

IPC分类号： H01L2976

CPC分类号： H01L29/495 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/41783 ,  H01L29/4941 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/78 ,  Y10S257/90

摘要： A semiconductor device includes a semiconductor substrate, a gate insulator film formed on a bottom surface and a side surface of a groove formed in the semiconductor substrate, a gate electrode having a lower portion buried in the groove on whose bottom and side surface the gate insulator film is formed, and an upper portion protruding a surface of said semiconductor substrate, and source region and a drain region formed on a surface of the semiconductor substrate in such a way as to sandwich the gate electrode. A thickness of the upper portion of the gate electrode protruding the surface of the semiconductor substrate is equal to or greater than twice a thickness of the lower portion of the gate electrode buried in the groove.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底的凹槽的底面和凹槽的侧面上的栅极绝缘体膜，栅电极，其下部埋设在沟槽中，栅极绝缘体的底部和侧表面上的栅极绝缘体 并且形成在半导体衬底的表面上的源极区域和漏极区域以夹着栅极电极的方式突出所述半导体衬底的表面的上部。 突出半导体衬底表面的栅电极的上部的厚度等于或大于埋在槽中的栅电极的下部的厚度的两倍。

公开(公告)号：US6054355A

公开(公告)日：2000-04-25

申请号：US105956

申请日：1998-06-29

申请人： Seiji Inumiya ,  Tomohiro Saito ,  Atsushi Yagishita ,  Katsuhiko Hieda ,  Toshihiko Iinuma

发明人： Seiji Inumiya ,  Tomohiro Saito ,  Atsushi Yagishita ,  Katsuhiko Hieda ,  Toshihiko Iinuma

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L29/495 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/4941 ,  H01L29/66537 ,  Y10S257/90

摘要： A method of manufacturing a semiconductor device comprises the steps of forming a first film and a second film on a semiconductor substrate, selectively removing the second film, the first film and a top portion of the semiconductor substrate to form a first groove, burying a first insulator film in the first groove to form an isolation region, patterning the second film surrounded by the isolation region to form a dummy gate layer, doping the semiconductor substrate with an impurity using the dummy gate layer as a mask, forming a second insulator film on the semiconductor substrate surrounded by the dummy gate layer and the first insulator film, removing the dummy gate layer and the first film to form a second groove, forming a gate insulator film on the semiconductor substrate in the second groove, and forming a gate electrode on the gate insulator film in the second groove.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一膜和第二膜，选择性地去除第二膜，第一膜和半导体衬底的顶部以形成第一槽， 在第一沟槽中形成绝缘体膜以形成隔离区域，对由隔离区域包围的第二膜进行构图以形成伪栅极层，使用伪栅极层作为掩模将杂质掺杂到半导体衬底上，形成第二绝缘膜 所述半导体基板被所述伪栅极层和所述第一绝缘膜包围，去除所述伪栅极层和所述第一膜以形成第二沟槽，在所述第二沟槽中的所述半导体基板上形成栅极绝缘膜，并且形成栅电极 第二槽中的栅极绝缘膜。

公开(公告)号：US5650339A

公开(公告)日：1997-07-22

申请号：US568973

申请日：1995-12-07

申请人： Tomohiro Saito ,  Minoru Takahashi ,  Atsushi Yagishita

发明人： Tomohiro Saito ,  Minoru Takahashi ,  Atsushi Yagishita

IPC分类号： H01L27/08 ,  H01L21/28 ,  H01L21/336 ,  H01L21/84 ,  H01L29/423 ,  H01L29/786 ,  H01L21/265

CPC分类号： H01L29/66772 ,  H01L21/28123 ,  H01L21/84 ,  H01L29/42384 ,  H01L29/78675

摘要： A semiconductor device includes an underlying layer formed by a first insulation layer, a plurality of island semiconductor layers formed on the first insulation layer, source and drain regions formed in each of the island semiconductor layers, a first gate electrode formed between the source and drain regions and formed on and insulated from the island semiconductor layer, a second insulation layer formed on the sides of the island semiconductor layer and along the periphery of the first gate electrode, the second insulation layer being higher than the surface of the island semiconductor layer and lower than the surface of the first gate electrode, and a second gate electrode formed over both the first gate electrode and the second insulation layer.

摘要翻译： 半导体器件包括由第一绝缘层形成的下层，形成在第一绝缘层上的多个岛状半导体层，形成在每个岛状半导体层中的源极和漏极区域，形成在源极和漏极之间的第一栅电极 区域，形成在岛状半导体层上并与岛半导体层绝缘;第二绝缘层，形成在岛状半导体层的侧面上并且沿着第一栅电极的周边，第二绝缘层高于岛状半导体层的表面， 低于第一栅电极的表面，以及形成在第一栅电极和第二绝缘层两者上的第二栅电极。

公开(公告)号：US20100035396A1

公开(公告)日：2010-02-11

申请号：US12588336

申请日：2009-10-13

申请人： Tomohiro Saito ,  Akio Kaneko ,  Atsushi Yagishita

发明人： Tomohiro Saito ,  Akio Kaneko ,  Atsushi Yagishita

IPC分类号： H01L21/336

CPC分类号： H01L29/66795 ,  H01L29/4908 ,  H01L29/785

摘要： This disclosure concerns a manufacturing method of a semiconductor device includes forming a Fin-type body on an insulation layer, the Fin-type body being made of a semiconductor material and having an upper surface covered with a protective film; forming a gate insulation film on side surfaces of the Fin-type body; depositing a gate electrode material so as to cover the Fin-type body; planarizing the gate electrode material; forming a gate electrode by processing the gate electrode material; depositing an interlayer insulation film so as to cover the gate electrode; exposing the upper surface of the gate electrode; depositing a metal layer on the upper surface of the gate electrode; siliciding the gate electrode by reacting the gate electrode with the metal layer; forming a trench on the upper surface of the protective film by removing an unreacted metal in the metal layer; and filling the trench with a conductor.

摘要翻译： 本公开涉及半导体器件的制造方法，包括在绝缘层上形成鳍状体，所述鳍状体由半导体材料制成，并且具有被保护膜覆盖的上表面; 在鳍型体的侧表面上形成栅极绝缘膜; 沉积栅电极材料以覆盖鳍型体; 平面化栅电极材料; 通过处理栅电极材料形成栅电极; 沉积层间绝缘膜以覆盖栅电极; 露出栅电极的上表面; 在栅电极的上表面上沉积金属层; 通过使栅电极与金属层反应来硅化栅电极; 通过去除金属层中的未反应金属在保护膜的上表面上形成沟槽; 并用导体填充沟槽。

公开(公告)号：US07198994B2

公开(公告)日：2007-04-03

申请号：US10991485

申请日：2004-11-19

申请人： Atsushi Yagishita ,  Tomohiro Saito

发明人： Atsushi Yagishita ,  Tomohiro Saito

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： Dummy gate patterns 111, 112 are formed on a silicon active layer 103 of an SOI substrate, and thereafter, these dummy gate patterns 111, 112 are removed to form gate grooves 130, 132. A threshold voltage of each transistor is adjusted by etching a silicon active layer 103 in any one of these gate, grooves 130, 132 to reduce a thickness of a portion constituting a channel region. This enables the enhancement of freedom degree and so on in circuit designing according to conditions.

摘要翻译： 在SOI衬底的硅有源层103上形成虚拟栅极图案111,112，然后去除这些虚拟栅极图案111,112以形成栅极沟槽130,132。通过蚀刻栅极图案111,112来调节每个晶体管的阈值电压 这些栅极，沟槽130,132中的任一个中的硅有源层103，以减小构成沟道区域的部分的厚度。 这样可以根据条件提高电路设计中的自由度等。

公开(公告)号：US06879001B2

公开(公告)日：2005-04-12

申请号：US10393017

申请日：2003-03-21

申请人： Atsushi Yagishita ,  Tomohiro Saito

发明人： Atsushi Yagishita ,  Tomohiro Saito

IPC分类号： H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： Dummy gate patterns 111, 112 are formed on a silicon active layer 103 of an SOI substrate, and thereafter, these dummy gate patterns 111, 112 are removed to form gate grooves 130, 132. A threshold voltage of each transistor is adjusted by etching a silicon active layer 103 in any one of these gate grooves 130, 132 to reduce a thickness of a portion constituting a channel region. This enables the enhancement of freedom degree and so on in circuit designing according to conditions.

摘要翻译： 在SOI衬底的硅有源层103上形成虚拟栅极图案111,112，然后去除这些虚拟栅极图案111,112以形成栅极沟槽130,132。通过蚀刻栅极图案111,112来调节每个晶体管的阈值电压 这些栅极沟槽130,132中的任何一个中的硅有源层103，以减小构成沟道区域的部分的厚度。 这样可以根据条件提高电路设计中的自由度等。

公开(公告)号：US09287050B2

公开(公告)日：2016-03-15

申请号：US13413889

申请日：2012-03-07

申请人： Tomohiro Saito

发明人： Tomohiro Saito

IPC分类号： H01L29/84 ,  H01G5/18 ,  B81C1/00

CPC分类号： H01G5/18 ,  B81B2201/018 ,  B81B2201/0221 ,  B81B2203/0109 ,  B81C1/00611 ,  B81C2201/0126

摘要： According to one embodiment, a MEMS includes a first electrode, a first auxiliary structure and a second electrode. The first electrode is provided on a substrate. The first auxiliary structure is provided on the substrate and adjacent to the first electrode. The first auxiliary structure is in an electrically floating state. The second electrode is provided above the first electrode and the first auxiliary structure, and is driven in a direction of the first electrode.

摘要翻译： 根据一个实施例，MEMS包括第一电极，第一辅助结构和第二电极。 第一电极设置在基板上。 第一辅助结构设置在基板上并与第一电极相邻。 第一辅助结构处于电浮动状态。 第二电极设置在第一电极和第一辅助结构之上，并且沿第一电极的方向被驱动。

公开(公告)号：US08905593B2

公开(公告)日：2014-12-09

申请号：US13601735

申请日：2012-08-31

申请人： Tomohiro Saito

发明人： Tomohiro Saito

IPC分类号： F21V13/04 ,  G02B19/00 ,  F21V5/02 ,  F21V7/00 ,  F21Y101/02 ,  F21V3/04

CPC分类号： F21V5/02 ,  F21V3/04 ,  F21V7/0091 ,  F21Y2115/10 ,  G02B19/0009 ,  G02B19/0028 ,  G02B19/0061

摘要： A luminous flux control member that controls travelling direction of light emitted from a light source includes an incident area, an emission area, and a plurality of projecting sections. The plurality of projecting sections are constituted by an inner area, an intermediate area, and a peripheral area defined in the radial direction, and a first specific projecting section disposed in the inner area is configured such that a planar section that is used to measure the height of the first specific projecting section and is perpendicular to the optical axis is connected to an inner peripheral end and an outer peripheral end of a base end portion of the first specific projecting section. The projecting sections other than the first specific projecting section, in principle, come into contact internally or externally with another projecting section other than the first specific projecting section.

摘要翻译： 控制从光源射出的光的行进方向的光束控制部件具有入射面积，发光面积，以及多个突出部。 多个突出部分由沿径向限定的内部区域，中间区域和周边区域构成，并且设置在内部区域中的第一特定突出部分被构造成使得用于测量 第一特定突出部的高度，与光轴垂直的高度与第一特定突出部的基端部的内周端和外周端连接。 原理上，除了第一特定突出部分之外的突出部分在内部或外部与除第一特定突出部分之外的另一个突出部分接触。

公开(公告)号：US08475618B2

公开(公告)日：2013-07-02

申请号：US13198867

申请日：2011-08-05

申请人： Mamo Matsumoto ,  Tomohiro Saito ,  Nobuhiro Ito

发明人： Mamo Matsumoto ,  Tomohiro Saito ,  Nobuhiro Ito

IPC分类号： B32B37/16

CPC分类号： H01L51/5246 ,  H01J9/241 ,  H01L51/525

摘要： A manufacturing method of a hermetic container includes an assembling step of assembling the hermetic container and a sealing step of sealing by first and second sealing materials. Thus, in a case where local heating light is scanned toward an already-sealed portion of the second sealing material, since a separation portion of an unsealed state is located between the already-sealed portion and a downstream end of scanning, a load due to expansion/contraction of a frame body is applied to the first sealing material which is present in the separation portion of the unsealed state. After then, since the local heating light is irradiated to the first sealing material to which the load has been applied so as to heat and melt it, the load is relieved, whereby it is possible to suppress deterioration of joining strength and airtightness of the hermetic container.

摘要翻译： 密封容器的制造方法包括组装密封容器的组装步骤和通过第一和第二密封材料密封的密封步骤。 因此，在向第二密封材料的已经密封的部分扫描局部加热光的情况下，由于未密封状态的分离部位于已经密封的部分和扫描的下游端之间，所以由于 将框体的伸缩进行施加到存在于未密封状态的分离部中的第一密封材料。 然后，由于局部加热光被照射到已经施加负载的第一密封材料上以加热和熔化，所以负载被释放，从而可以抑制密封件的接合强度和气密性的劣化 容器。