公开(公告)号：US20120267697A1

公开(公告)日：2012-10-25

申请号：US13091292

申请日：2011-04-21

申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

IPC分类号： H01L27/06 ,  H01L21/8242

CPC分类号： H01L27/10894 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/1207 ,  H01L29/66181 ,  H01L29/945

摘要： A semiconductor chip has an embedded dynamic random access memory (eDRAM) in an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM deep trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. Retention time and performance of the eDRAM is controlled by applying a voltage to the independently voltage controlled silicon region.

摘要翻译： 半导体芯片在独立电压控制的硅​​区域中具有嵌入式动态随机存取存储器（eDRAM），该区域是用于控制eDRAM深沟槽电容器的电容值和覆盖独立电压控制的硅​​区域的场效应晶体管的阈值电压的电路元件。 eDRAM的保留时间和性能通过向独立的电压控制的硅​​区域施加电压来控制。

公开(公告)号：US07868391B2

公开(公告)日：2011-01-11

申请号：US12478098

申请日：2009-06-04

申请人： Phil Christopher Felice Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Kelly L. Williams

发明人： Phil Christopher Felice Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Kelly L. Williams

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/62

CPC分类号： H01L27/092 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/0688

摘要： A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect transistor) of a first doping type, the first FET having first source/drain regions in a semiconductor substrate, or in a well in the semiconductor substrate. The single gate electrode has a second gate dielectric between the gate electrode and a body of a second FET of opposite doping to the first FET. Second source/drain regions of the second FET are formed from epitaxial layers grown over the first source/drain regions.

摘要翻译： 具有单个栅电极的3-D（三维）逆变器。 单栅电极在栅电极和第一掺杂类型的第一FET（场效应晶体管）的主体之间具有第一栅极电介质，第一FET在半导体衬底中具有第一源/漏区，或在第 半导体衬底。 单栅电极在栅电极和与第一FET相反掺杂的第二FET的本体之间具有第二栅极电介质。 第二FET的第二源极/漏极区域由在第一源极/漏极区域上生长的外延层形成。

公开(公告)号：US06613841B2

公开(公告)日：2003-09-02

申请号：US10058894

申请日：2002-01-28

申请人： Kelly L. Williams

发明人： Kelly L. Williams

IPC分类号： C08L2300

CPC分类号： C08L23/0815 ,  C08L2205/02 ,  C08L2205/025 ,  C08L2666/04

摘要： A process for making MD (machine direction) oriented polyethylene film is disclosed. The process comprises blending a high-molecular weight, medium-density polyethylene (HMW MDPE) and a linear low-density polyethylene (LLDPE), converting the blend into a thick film, and orienting the thick film into a thinner film in the machine direction. The resulting film has high modulus, high gloss, low haze, and relatively high MD tear and dart impact.

摘要翻译： 公开了一种制造MD（机器方向）取向聚乙烯薄膜的方法。 该方法包括混合高分子量中密度聚乙烯（HMW MDPE）和线性低密度聚乙烯（LLDPE），将共混物转化为厚膜，并将厚膜定向成机器方向上的薄膜 。 所得膜具有高模量，高光泽度，低雾度和相对高的MD撕裂和飞镖冲击。

公开(公告)号：US20130341733A1

公开(公告)日：2013-12-26

申请号：US13532422

申请日：2012-06-25

申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets ,  Gregory J. Uhlmann ,  Kelly L. Williams

发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets ,  Gregory J. Uhlmann ,  Kelly L. Williams

IPC分类号： H01L27/088 ,  H01L21/20

CPC分类号： H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L27/1211

摘要： A plural differential pair may include a first semiconductor fin having first and second drain areas. First and second body areas may be disposed on the fin between the first and second drain areas. A source area may be disposed on the fin between the first and second body areas. The plural differential pair may include a first pair of fin field effect (FinFET) transistors and a second pair of FinFET transistors. The plural differential pair may include first and second top fin areas projecting from respective portions of a top side of the first and second body areas of the fin. The first and second top fin areas may each have a width that is wider than the first and second body areas of the fin.

摘要翻译： 多个差分对可以包括具有第一和第二漏极区域的第一半导体鳍片。 第一和第二主体区域可以设置在第一和第二排水区域之间的翅片上。 源区域可以设置在第一和第二身体区域之间的翅片上。 多个差分对可以包括第一对鳍场效应（FinFET）晶体管和第二对FinFET晶体管。 多个差分对可以包括从翅片的第一和第二主体区域的顶侧的相应部分突出的第一和第二顶部翅片区域。 第一和第二顶鳍区域可以各自具有比翅片的第一和第二身体区域宽的宽度。

公开(公告)号：US20130341720A1

公开(公告)日：2013-12-26

申请号：US13533484

申请日：2012-06-26

申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

IPC分类号： H01L29/78 ,  G06F17/50 ,  H01L21/336

CPC分类号： H01L29/4238 ,  H01L29/517 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7831 ,  H01L29/7848

摘要： A method and circuit for implementing field effect transistors (FETs) having a gate within a gate utilizing a replacement metal gate process (RMGP), and a design structure on which the subject circuit resides are provided. A field effect transistor utilizing a RMGP includes a sacrificial gate in a generally central metal gate region on a dielectric layer on a substrate, a source and drain formed in the substrate, a pair of dielectric spacers, a first metal gate and a second metal gate replacing the sacrificial gate inside the central metal gate region, and a second gate dielectric layer separating the first metal gate and the second metal gate. A respective electrical contact is formed on opposite sides of the central metal gate region for respectively electrically connecting the first metal gate and the second metal gate to a respective voltage.

摘要翻译： 一种用于利用替换金属栅极处理（RMGP）来实现在栅极内具有栅极的场效应晶体管（FET）的方法和电路，以及设置有该电路所在的设计结构。 利用RMGP的场效应晶体管包括在衬底上的介电层上的大致中心的金属栅极区域中的牺牲栅极，在衬底中形成的源极和漏极，一对电介质间隔物，第一金属栅极和第二金属栅极 替换中心金属栅极区域内的牺牲栅极，以及分离第一金属栅极和第二金属栅极的第二栅极介电层。 在中心金属栅极区域的相对侧上形成相应的电触点，用于将第一金属栅极和第二金属栅极电连接到相应的电压。

公开(公告)号：US20130313441A1

公开(公告)日：2013-11-28

申请号：US13478821

申请日：2012-05-23

申请人： Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

发明人： Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

IPC分类号： G01T1/17

CPC分类号： G01T1/247

摘要： An apparatus includes a first radiation detector to generate a first signal when a first radiation level is exceeded and a second radiation detector to generate a second signal when a second radiation level is exceeded. The second radiation level is greater than the first radiation level. A first circuit is susceptible to soft errors at the first radiation level and a second circuit is susceptible to soft errors at the second radiation level. A control unit may suspend use of the first circuit and activate use of the second circuit if the first signal is received and the second signal is not received. The first and second circuits may be memory cells or logic circuits.

摘要翻译： 一种装置包括：当超过第一辐射水平时产生第一信号的第一辐射检测器和当超过第二辐射水平时产生第二信号的第二辐射检测器。 第二辐射水平大于第一辐射水平。 第一电路易受第一辐射电平处的软错误的影响，第二电路易受第二辐射电平处的软错误的影响。 如果接收到第一信号并且没有接收到第二信号，则控制单元可以暂停使用第一电路并激活第二电路的使用。 第一和第二电路可以是存储器单元或逻辑电路。

公开(公告)号：US08456187B2

公开(公告)日：2013-06-04

申请号：US13091243

申请日：2011-04-21

申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

IPC分类号： H03K19/00

CPC分类号： H01L21/761 ,  H01L21/76283

摘要： A method and circuits for implementing a temporary disable function at indeterminate times of circuitry to be protected in a semiconductor chip, such as in an integrated circuit or a system on a chip (SOC) by modulating threshold voltage shifts of a timing sensitive circuit, and a design structure on which the subject circuit resides are provided. The timing sensitive circuit is designed to be sensitive to threshold-voltage shifts and is placed over an independently voltage controlled silicon region. Upon startup, the independently voltage controlled silicon region is grounded, and then is left floating. Each time a hack attempt or predefined functional oddity is detected, charge is applied onto the independently voltage controlled silicon region. After a defined charge has accumulated, the device threshold voltages in the timing sensitive circuit above the independently voltage controlled silicon region are modulated causing the timing-sensitive circuit to fail.

摘要翻译： 一种用于通过调制定时敏感电路的阈值电压偏移来在诸如集成电路或芯片上的系统（SOC）的半导体芯片的不确定时间来实现临时禁用功能的方法和电路，以及 提供了主题电路所在的设计结构。 时序敏感电路设计为对阈值电压偏移敏感，并置于独立的电压控制硅区域上。 启动时，独立的电压控制硅区域接地，然后悬空。 每次检测到黑客尝试或预定义的功能奇偶性时，将电荷施加到独立的受控硅区域。 在定义的电荷累积之后，对独立电压控制的硅​​区域之上的定时敏感电路中的器件阈值电压进行调制，使定时敏感电路失效。

公开(公告)号：US20120268160A1

公开(公告)日：2012-10-25

申请号：US13091243

申请日：2011-04-21

申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

IPC分类号： H02H5/00 ,  H01L21/762

CPC分类号： H01L21/761 ,  H01L21/76283

摘要： A method and circuits for implementing a temporary disable function at indeterminate times of circuitry to be protected in a semiconductor chip, such as in an integrated circuit or a system on a chip (SOC) by modulating threshold voltage shifts of a timing sensitive circuit, and a design structure on which the subject circuit resides are provided. The timing sensitive circuit is designed to be sensitive to threshold-voltage shifts and is placed over an independently voltage controlled silicon region. Upon startup, the independently voltage controlled silicon region is grounded, and then is left floating. Each time a hack attempt or predefined functional oddity is detected, charge is applied onto the independently voltage controlled silicon region. After a defined charge has accumulated, the device threshold voltages in the timing sensitive circuit above the independently voltage controlled silicon region are modulated causing the timing-sensitive circuit to fail.

摘要翻译： 一种用于通过调制定时敏感电路的阈值电压偏移来在诸如集成电路或芯片上的系统（SOC）的半导体芯片的不确定时间来实现临时禁用功能的方法和电路，以及 提供了主题电路所在的设计结构。 时序敏感电路设计为对阈值电压偏移敏感，并置于独立的电压控制硅区域上。 启动时，独立的电压控制硅区域接地，然后悬空。 每次检测到黑客尝试或预定义的功能奇偶性时，将电荷施加到独立的受控硅区域。 在定义的电荷累积之后，对独立电压控制的硅​​区域之上的定时敏感电路中的器件阈值电压进行调制，使定时敏感电路失效。

公开(公告)号：US20120216301A1

公开(公告)日：2012-08-23

申请号：US13031748

申请日：2011-02-22

申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

IPC分类号： G06F11/00

CPC分类号： G06F21/556

摘要： A method and circuits for implementing a hacking detection and block function at indeterminate times, and a design structure on which the subject circuit resides are provided. A circuit includes an antenna wrapped around a dynamic bus inside circuitry to be protected. The antenna together with the dynamic bus node is designed so an average bus access activates a field effect transistor (FET) that is connected to a capacitor. The FET drains the capacitor in a specified number of activations by the antenna. The capacitor has a leakage path to a voltage supply rail VDD that charges the capacitor back high after a time, such as ten to one hundred cycles, of the dynamic bus being quiet. The capacitor provides a hacking detect signal for temporarily blocking operation of the circuitry to be protected responsive to determining that the dynamic bus is more active than functionally expected.

摘要翻译： 一种用于在不确定时间实现黑客检测和阻止功能的方法和电路，以及设置有被摄体电路所在的设计结构。 一个电路包括一个围绕要保护的电路内的动态总线的天线。 天线与动态总线节点一起被设计成平均总线访问激活连接到电容器的场效应晶体管（FET）。 FET通过天线在指定数量的激活中排出电容器。 电容器具有到电压供应轨VDD的泄漏路径，该电压供应轨VDD在动态总线静止的时间（如10到100个周期）之后将电容器充电回来。 电容器提供黑客检测信号，以便响应于确定动态总线比功能预期更有活力来暂时阻止要被保护的电路的操作。

公开(公告)号：US08034461B2

公开(公告)日：2011-10-11

申请号：US11054202

申请日：2005-02-09

申请人： D. Ryan Breese ,  Kelly L. Williams ,  Charles S. Holland ,  Mark P. Mack

发明人： D. Ryan Breese ,  Kelly L. Williams ,  Charles S. Holland ,  Mark P. Mack

IPC分类号： B32B11/08 ,  B32B27/08

CPC分类号： B32B27/08 ,  B29C55/023 ,  B29C55/06 ,  B29K2023/0625 ,  B29K2023/0641 ,  B29K2023/065 ,  B29K2023/083 ,  B32B7/005 ,  B32B7/02 ,  B32B27/18 ,  B32B27/32 ,  B32B2250/242 ,  B32B2264/0214 ,  B32B2307/54 ,  B32B2307/558 ,  B32B2307/5825 ,  B32B2553/00 ,  Y10S428/91 ,  Y10T428/31913

摘要： A method for making multilayer thin films is disclosed. The method of comprises orienting a thick multilayer film in the machine direction at a drawdown ratio effective to produce a multilayer thin film. The thick multilayer film has a thickness within the range of 1 mil to 5 mils and comprises at least one layer of a linear low density polyethylene (LLDPE) and at least one layer of a high density polyethylene (HDPE) or a medium density polyethylene (MDPE).

摘要翻译： 公开了制备多层薄膜的方法。 该方法包括以有效产生多层薄膜的拉伸比在机器方向上定向厚多层膜。 厚多层膜的厚度在1密耳至5密耳的范围内，并且包括至少一层线性低密度聚乙烯（LLDPE）和至少一层高密度聚乙烯（HDPE）或中密度聚乙烯（ MDPE）。