公开(公告)号：US09276014B2

公开(公告)日：2016-03-01

申请号：US14852810

申请日：2015-09-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Seongyeol Yoo ,  Youngsuk Song ,  Heecheol Kim ,  Seungjin Choi

IPC: H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  G02F1/1362 ,  G02F1/1368 ,  G02F1/1343 ,  H01L29/24 ,  H01L23/522 ,  H01L23/31

CPC classification number: H01L27/1225 ,  G02F1/13439 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134372 ,  H01L21/77 ,  H01L23/3171 ,  H01L23/5226 ,  H01L27/124 ,  H01L27/1259 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/24 ,  H01L29/7869 ,  H01L2224/24 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/92244

Abstract: An array substrate, a method of fabricating the same, and a liquid crystal display device are disclosed. The method comprises: sequentially forming a first transparent conductive material layer, an insulation material layer, a semiconductor material layer and a photoresist layer on a substrate base and forming patterns including a gate line, a gate, a gate insulation layer, a semiconductor layer and a first transparent electrode by patterning process; forming a passivation layer and forming a source via and a drain via connected to the semiconductor layer in the passivation layer; sequentially forming a second transparent conductive material layer and a source-drain metal layer and forming patterns including a source, a drain and a second transparent electrode by patterning process, the gate insulation layer is formed only on the gate and the gate line, the source and the drain include stacked second transparent conductive material layer and source-drain metal layer.

公开(公告)号：US20150205564A1

公开(公告)日：2015-07-23

申请号：US14361879

申请日：2013-12-09

Applicant: BOE TECHNOLOGY GROUP CO., LTD

Inventor： Chao Xu ,  Chunfang Zhang ,  Yan Wei ,  Heecheol Kim

IPC: G06F3/14

CPC classification number: G06F3/1446 ,  G02F1/13336 ,  G06F3/1431 ,  Y10T29/49117 ,  Y10T428/24802

Abstract: A substrate provided with alignment marks, a display screen, a splicing screen and an alignment method of splicing screen, in which, the splicing screen includes at least two display screens with alignment marks. A substrate of the display screen is provided with at least two alignment marks, and different alignment marks have a height difference therebetween which is larger or equal to a standard difference value. A narrow bezel splicing of display screens can be achieved by setting the alignment marks with different heights.

Abstract translation: 具有对准标记的基板，显示屏幕，拼接屏幕和拼接屏幕的对准方法，其中拼接屏幕包括具有对准标记的至少两个显示屏幕。 显示屏的基板设置有至少两个对准标记，并且不同的对准标记之间的高度差大于或等于标准差值。 可以通过设置不同高度的对准标记来实现显示屏的窄边框拼接。

公开(公告)号：US09070599B2

公开(公告)日：2015-06-30

申请号：US14361396

申请日：2013-10-31

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Heecheol Kim ,  Youngsuk Song ,  Seongyeol Yoo ,  Seungjin Choi

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/786 ,  H01L21/283 ,  H01L21/3213 ,  H01L23/31 ,  H01L29/10 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L27/124 ,  G02F1/1362 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2201/40 ,  H01L21/283 ,  H01L21/32133 ,  H01L21/76802 ,  H01L23/3171 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/1033 ,  H01L29/41733 ,  H01L29/4175 ,  H01L29/66765 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An array substrate, a manufacturing method thereof and a display device are provided, and the array substrate comprises: a substrate (1); a plurality of data lines (16), formed on the substrate and extending in a first direction; a plurality of gate lines (15), formed on the substrate (1), crossing the plurality of data lines (15), and extending in a second direction perpendicular to the first direction; a plurality of pixel regions, defined by the plurality of gate lines (15) and the plurality of data lines (15) crossing each other and arranged in a matrix form, wherein each of the pixel regions is provided with a thin film transistor and a pixel electrode (12), wherein, the thin film transistor comprises: a gate electrode (2), connected with one of the plurality of gate lines (15); a gate insulating layer (3), provided above the gate line (15) and the gate electrode (2); an active layer (5), formed on the gate insulating layer (3) and disposed corresponding to the gate electrode (2); a drain electrode (8) and a source electrode (9), disposed opposite to each other above the active layer (5) and having a channel region of the thin film transistor therebetween; a filling layer (4), provided between the gate electrode (2) and the gate line (15) connected with the gate electrode, and the drain and source electrodes (8) and (9); and a passivation layer (10), provided on the source electrode (9), the drain electrode (8) and the active layer (5), wherein at a position directly facing the gate line (15), the passivation layer (10) is provided with a passivation layer through hole (11) configured to perform a connection between the drain electrode (8) and the pixel electrode (12).

Abstract translation: 提供阵列基板，其制造方法和显示装置，并且阵列基板包括：基板（1）; 多个数据线（16），形成在所述基板上并沿第一方向延伸; 多个栅极线（15），形成在所述基板（1）上，与所述多条数据线（15）交叉并且沿与所述第一方向垂直的第二方向延伸; 由多个栅极线（15）和多条数据线（15）限定的多个像素区域，彼此交叉并以矩阵形式布置，其中每个像素区域设置有薄膜晶体管和 像素电极（12），其中，所述薄膜晶体管包括：栅电极（2），与所述多条栅极线（15）之一连接; 栅极绝缘层（3），设置在栅极线（15）和栅电极（2）之上; 形成在所述栅极绝缘层（3）上并对应于所述栅极（2）设置的有源层（5）; 漏电极（8）和源电极（9），其在有源层（5）上方相对设置，并且在其间具有薄膜晶体管的沟道区域; 设置在与栅极电极连接的栅电极（2）和栅极线（15）之间的填充层（4）以及漏极和源电极（8）和（9）; 以及设置在源电极（9），漏极（8）和有源层（5）上的钝化层（10），其中在直接面向栅极线（15）的位置处，钝化层（10） 设置有被配置为执行漏电极（8）和像素电极（12）之间的连接的钝化层通孔（11）。

公开(公告)号：US09040344B2

公开(公告)日：2015-05-26

申请号：US13984090

申请日：2012-12-13

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Seungjin Choi ,  Heecheol Kim ,  Youngsuk Song ,  Seongyeol Yoo

IPC: H01L21/02 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/7869 ,  G02F1/134363 ,  G02F2001/134372 ,  G02F2001/136231 ,  H01L21/02565 ,  H01L21/02664 ,  H01L27/1203 ,  H01L27/1225

Abstract: A method for fabricating array substrate, an array substrate and a display device. The method for fabricating the array substrate comprises forming a thin film transistor, a first transparent electrode (14) and a second transparent electrode (19), wherein a multi dimensional electric field is created by the first transparent electrode (17) and the second transparent electrode (19), wherein forming the first transparent electrode (17) comprises: forming a metal oxide film presenting semiconductor properties; forming the first transparent electrode (17) by subjecting a portion of the metal oxide film to metallization treatment, and forming a semiconductor active layer (141) from a portion which is not subjected to the metallization treatment.

Abstract translation: 阵列基板，阵列基板和显示装置的制造方法。 制造阵列基板的方法包括形成薄膜晶体管，第一透明电极（14）和第二透明电极（19），其中由第一透明电极（17）和第二透明电极（17）产生多维电场 电极（19），其中形成所述第一透明电极（17）包括：形成呈现半导体特性的金属氧化物膜; 通过对金属氧化物膜的一部分进行金属化处理来形成第一透明电极（17），并且从未进行金属化处理的部分形成半导体活性层（141）。

公开(公告)号：US20150028342A1

公开(公告)日：2015-01-29

申请号：US14361396

申请日：2013-10-31

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Heecheol Kim ,  Youngsuk Song ,  Seongyeol Yoo ,  Seungjin Choi

IPC: H01L27/12 ,  H01L29/417 ,  H01L21/3213 ,  H01L21/283 ,  H01L23/31 ,  H01L29/10

CPC classification number: H01L27/124 ,  G02F1/1362 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2201/40 ,  H01L21/283 ,  H01L21/32133 ,  H01L21/76802 ,  H01L23/3171 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/1033 ,  H01L29/41733 ,  H01L29/4175 ,  H01L29/66765 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An array substrate, a manufacturing method thereof and a display device are provided, and the array substrate comprises: a substrate (1); a plurality of data lines (16), formed on the substrate and extending in a first direction; a plurality of gate lines (15), formed on the substrate (1), crossing the plurality of data lines (15), and extending in a second direction perpendicular to the first direction; a plurality of pixel regions, defined by the plurality of gate lines (15) and the plurality of data lines (15) crossing each other and arranged in a matrix form, wherein each of the pixel regions is provided with a thin film transistor and a pixel electrode (12), wherein, the thin film transistor comprises: a gate electrode (2), connected with one of the plurality of gate lines (15); a gate insulating layer (3), provided above the gate line (15) and the gate electrode (2); an active layer (5), formed on the gate insulating layer (3) and disposed corresponding to the gate electrode (2); a drain electrode (8) and a source electrode (9), disposed opposite to each other above the active layer (5) and having a channel region of the thin film transistor therebetween; a filling layer (4), provided between the gate electrode (2) and the gate line (15) connected with the gate electrode, and the drain and source electrodes (8) and (9); and a passivation layer (10), provided on the source electrode (9), the drain electrode (8) and the active layer (5), wherein at a position directly facing the gate line (15), the passivation layer (10) is provided with a passivation layer through hole (11) configured to perform a connection between the drain electrode (8) and the pixel electrode (12).

Abstract translation: 提供阵列基板，其制造方法和显示装置，并且阵列基板包括：基板（1）; 多个数据线（16），形成在所述基板上并沿第一方向延伸; 多个栅极线（15），形成在所述基板（1）上，与所述多条数据线（15）交叉并且沿与所述第一方向垂直的第二方向延伸; 由多个栅极线（15）和多条数据线（15）限定的多个像素区域，彼此交叉并以矩阵形式布置，其中每个像素区域设置有薄膜晶体管和 像素电极（12），其中，所述薄膜晶体管包括：栅电极（2），与所述多条栅极线（15）之一连接; 栅极绝缘层（3），设置在栅极线（15）和栅电极（2）之上; 形成在所述栅极绝缘层（3）上并对应于所述栅极（2）设置的有源层（5）; 漏电极（8）和源电极（9），其在有源层（5）上方相对设置，并且在其间具有薄膜晶体管的沟道区域; 设置在与栅极电极连接的栅电极（2）和栅极线（15）之间的填充层（4）以及漏极和源电极（8）和（9）; 以及设置在源电极（9），漏极（8）和有源层（5）上的钝化层（10），其中在直接面向栅极线（15）的位置处，钝化层（10） 设置有被配置为执行漏电极（8）和像素电极（12）之间的连接的钝化层通孔（11）。

公开(公告)号：US20140175446A1

公开(公告)日：2014-06-26

申请号：US14139834

申请日：2013-12-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chao Xu ,  Heecheol Kim

IPC: H01L27/12

CPC classification number: H01L27/1259 ,  H01L27/1255

Abstract: An array substrate includes a GOA circuit area and a display area, the GOA circuit area includes a TFT area and a lead-wire area, the display area includes a data line and a gate line. The GOA circuit area is provided with at least one first via and at least one second via, a data-line metal layer is disposed at the bottom of the at least one first via, and a gate-line metal layer is disposed at the bottom of the at least one second via. The GOA circuit area further includes a first electrode and a second electrode, the data-line metal layer is electrically connected to one electrode through the at least one first via, the gate-line metal layer is electrically connected to the other electrode through the at least one second via, such that a capacitor is formed between the first electrode and the second electrode.

Abstract translation: 阵列基板包括GOA电路区域和显示区域，GOA电路区域包括TFT区域和引线区域，显示区域包括数据线和栅极线。 GOA电路区域设置有至少一个第一通孔和至少一个第二通孔，数据线金属层设置在至少一个第一通孔的底部，并且栅极金属层设置在底部 的至少一个第二通孔。 所述GOA电路区域还包括第一电极和第二电极，所述数据线金属层通过所述至少一个第一通孔电连接到一个电极，所述栅极线金属层通过所述至少一个第一通孔电连接到另一个电极 至少一秒钟的通孔，使得在第一电极和第二电极之间形成电容器。

公开(公告)号：US20140159022A1

公开(公告)日：2014-06-12

申请号：US14105145

申请日：2013-12-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Youngsuk SONG ,  Seongyeol Yoo ,  Seungjin Choi ,  Heecheol Kim

IPC: H01L27/32 ,  H01L51/56

CPC classification number: H01L27/3248 ,  H01L27/3206 ,  H01L27/322 ,  H01L27/3258 ,  H01L27/3272 ,  H01L51/5209 ,  H01L51/5265 ,  H01L51/5271 ,  H01L51/56 ,  H01L2251/5315

Abstract: This invention provides an array substrate, a method for fabricating the same, and an OLED display device, which can solve the technical problem that the existing OLED display device has low luminous efficiency. Each pixel unit of the array substrate comprises: a TFT drive layer; an OLED further away from the substrate than the TFT drive layer and driven by it, the OLED sequentially comprises a first electrode, a light emitting layer, and a transparent second electrode, wherein the first electrode is a reflection layer, or the first electrode is transparent and has a reflection layer disposed thereunder; a transflective layer further away from the substrate than the OLED and forming a microcavity structure with the reflection layer; and a color filter film disposed between the OLED and the transflective layer and located in the microcavity structure. The present invention is particularly suitable for a WOLED display device.

Abstract translation: 本发明提供阵列基板，其制造方法和OLED显示装置，其可以解决现有的OLED显示装置的发光效率低的技术问题。 阵列基板的每个像素单元包括：TFT驱动层; OLED比TFT驱动层更远离OLED驱动的OLED，OLED顺序地包括第一电极，发光层和透明的第二电极，其中第一电极是反射层，或者第一电极是 透明并具有设置在其下面的反射层; 比OLED更远离衬底的半透反射层，并与反射层形成微腔结构; 以及设置在OLED和透反射层之间并且位于微腔结构中的滤色膜。 本发明特别适用于WOLED显示装置。

公开(公告)号：US20140125909A1

公开(公告)日：2014-05-08

申请号：US13703567

申请日：2012-09-28

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Heecheol Kim ,  Chao Xu

IPC: G02F1/1362 ,  H01L27/12

CPC classification number: G02F1/136209 ,  G02F1/134309 ,  G02F2001/134318 ,  G02F2001/134381 ,  G02F2001/136218 ,  G02F2201/40 ,  H01L27/124

Abstract: Embodiments of the present invention disclose a pixel unit, an array substrate, a liquid crystal panel, a display device and a manufacturing method thereof. The pixel unit comprises a thin film transistor, a pixel electrode and a common electrode, the thin film transistor comprising a gate electrode, a gate insulating layer provided on the gate electrode, an active layer provided on the gate insulating layer, a source electrode and a drain electrode provided on the active layer, and a passivation layer provided on the source electrode and the drain electrode; wherein the common electrode is provided directly on the passivation layer; and the pixel electrode is provided under the passivation layer and is connected to the drain electrode of the thin film transistor. For the array substrate, the liquid crystal panel, the display device and the manufacturing method thereof, it is possible to increase view angles, lower power consumption, and increase aperture ratio, thereby improving display quality.

Abstract translation: 本发明的实施例公开了像素单元，阵列基板，液晶面板，显示装置及其制造方法。 像素单元包括薄膜晶体管，像素电极和公共电极，薄膜晶体管包括栅极电极，设置在栅极电极上的栅极绝缘层，设置在栅极绝缘层上的有源层，源极和 设置在所述有源层上的漏电极和设置在所述源电极和所述漏电极上的钝化层; 其中所述公共电极直接设置在所述钝化层上; 并且像素电极设置在钝化层下方并连接到薄膜晶体管的漏电极。 对于阵列基板，液晶面板，显示装置及其制造方法，可以增加视角，降低功耗并增加开口率，从而提高显示质量。

公开(公告)号：US11322063B2

公开(公告)日：2022-05-03

申请号：US16082071

申请日：2018-01-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Shuai Chen ,  Zhi Zhang ,  Xiuzhu Tang ,  Heecheol Kim ,  Xing Dong ,  Zhenguo Tian ,  Shuang Hu ,  Taoliang Tang ,  Jingpeng Zhao

IPC: G09G3/20

Abstract: A scan driving circuit and a driving method thereof, and a display device are disclosed. The scan driving circuit includes: a control circuit, a scanning circuit group and a first processing circuit group. The control circuit is configured to generate and output a keyword signal to the first processing circuit group, to control a scan order of respective scanning circuits in the scanning circuit group; the first processing circuit group is configured to generate a scan enable signal according to the keyword signal, and output the scan enable signal to a scanning circuit corresponding to the keyword signal in the scanning circuit group.

公开(公告)号：US11232846B2

公开(公告)日：2022-01-25

申请号：US16191746

申请日：2018-11-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Zhuo Xu ,  Yuanbo Zhang ,  Yajie Bai ,  Heecheol Kim ,  Peng Liang ,  Hailong Wu ,  Yi Dan

IPC: G11C19/00 ,  G11C19/28 ,  G09G3/20

Abstract: The present disclosure provides a gate drive unit, a driving method thereof and a gate drive circuit. The gate drive unit includes a shift register and a plurality of output control modules. Each of the output control modules is connected to a corresponding clock scanning signal line and a corresponding first scanning signal output terminal, respectively. Each of the output control modules includes a first output control submodule and an output reset submodule. The first output control submodule is connected to a signal output terminal of the shift register, the corresponding clock scanning signal line and the corresponding first scanning signal output terminal, and configured to send a clock scanning signal of the corresponding clock scanning signal line to the corresponding first scanning signal output terminal, under control of a signal outputted by the signal output terminal of the shift register.