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公开(公告)号：US20100044592A1
公开(公告)日：2010-02-25
申请号：US12610630
申请日：2009-11-02
CPC分类号： B23K26/0626 , B23K26/0608 , H01L21/26513 , H01L21/2686
摘要： A system for configuring and utilizing J electromagnetic radiation sources (J≧2) to serially irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I≧2; J≧I) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. In each of I independent exposure steps, the I stacks are concurrently exposed to radiation from the J sources. Vi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i in exposure step i (i=1, . . . , I). t(i) and Pt(i) are computed such that: Vi is maximal through deployment of source t(i) as compared with deployment of any other source for i=1, . . . , I; and an error E being a function of |V1−S1|, |V2−S2|, . . . , |VI−SI| is about minimized with respect to Pi (i=1, . . . , I).
摘要翻译： 一种用于配置和利用J电磁辐射源（J≥2）以串行照射衬底的系统。 每个源具有不同的发射辐射的波长和角分布的功能。 基板包括基层和I堆叠（I≥2;J≥I）。 Pj表示来自源j的每个堆叠上相同的源特定的正常入射能量通量。 在I独立暴露步骤中，I堆叠同时暴露于来自J源的辐射。 Vi和Si分别表示在曝光步骤i（i = 1，...，I）中通过堆叠i传输到衬底中的实际和目标能量通量。 计算t（i）和Pt（i），使得：与部署i = 1的任何其他源相比，通过部署源t（i），Vi最大。 。 。 ， 一世; 并且误差E是| V1-S1 |，| V2-S2 |的函数。 。 。 ，| VI-SI | 相对于Pi（i = 1，...，I）被最小化。
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公开(公告)号：US07473593B2
公开(公告)日：2009-01-06
申请号：US11275514
申请日：2006-01-11
IPC分类号： H01L21/336
CPC分类号： H01L29/66477 , H01L21/26506 , H01L21/28052 , H01L21/28114 , H01L21/28518 , H01L29/1083 , H01L29/42376 , H01L29/66507 , H01L29/6659 , H01L29/66772 , H01L29/66795 , H01L29/785 , H01L29/78654
摘要： A method for forming a semiconductor transistor with an expanded top portion of a gate The gate is expanded through implanting atoms in the top portion of transistor's gate electrode region. The transistor formed includes a semiconductor region having two source/drain regions and a gate dielectric region formed on the channel region between the source/drain regions. The gate electrode region is formed on the gate dielectric region. The gate electrode region is formed such that it is electrically insulated from the channel region by the gate dielectric region. The top of the gate electrode region formed is wider than the bottom of the gate electrode region.
摘要翻译： 用于形成具有扩大的栅极顶部的半导体晶体管的方法通过在晶体管的栅电极区域的顶部中注入原子来扩展栅极。 所形成的晶体管包括具有两个源极/漏极区域和形成在源极/漏极区域之间的沟道区域上的栅极电介质区域的半导体区域。 栅极区域形成在栅极电介质区域上。 栅电极区域形成为通过栅极电介质区域与沟道区域电绝缘。 所形成的栅极电极区域的顶部比栅电极区域的底部宽。
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公开(公告)号：US20080213964A1
公开(公告)日：2008-09-04
申请号：US12037113
申请日：2008-02-26
IPC分类号： H01L21/336
CPC分类号： H01L29/42384 , H01L29/66772 , H01L29/78654
摘要： A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.
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公开(公告)号：US20080169833A1
公开(公告)日：2008-07-17
申请号：US11622040
申请日：2007-01-11
IPC分类号： H03K19/00
CPC分类号： G06F21/75
摘要： An anti-counterfeiting circuit that is incorporated into an authentic integrated circuit (IC) design, which induces a random failure in a counterfeited IC when the counterfeit IC is manufactured from a reverse-engineered authentic IC. The anti-counterfeiting circuit uses two signals of differing frequencies, which activate a disrupt signal when the two signals meet a predetermined failure criteria, for example, equivalent rising edges. The disrupt signal causes a signal gate or similar element within the counterfeited IC to fail, disrupt, or in some way change a designed behavior of the IC. The disrupt signal may be reset so that the failure will occur again when predetermined failure criteria are met. The authentic IC functions according to design because at least one of the elements in the anti-counterfeit circuit is a camouflage circuit, thus, in an authentic IC the anti-counterfeit circuit is not operatively coupled.
摘要翻译： 一种防伪电路，其被并入真正的集成电路（IC）设计中，当假冒IC由逆向工程认证IC制造时，其引起假冒IC中的随机故障。 防伪电路使用两个不同频率的信号，当两个信号满足预定的故障标准（例如等效的上升沿）时，该信号激活中断信号。 该扰乱信号导致伪造IC内的信号门或类似元件故障，中断或以某种方式改变IC的设计行为。 可以复位中断信号，以便在满足预定的故障标准时再次发生故障。 由于防伪电路中的至少一个元件是伪装电路，所以可信赖的IC功能根据设计，因此，在可靠的IC中，防伪电路不可操作地耦合。
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公开(公告)号：US20080142806A1
公开(公告)日：2008-06-19
申请号：US11610533
申请日：2006-12-14
IPC分类号： H01L29/04
CPC分类号： H01L29/785 , H01L21/823821 , H01L27/0924 , H01L29/66795
摘要： A semiconductor device. The device including: a planar FET formed in a single crystal-silicon substrate, the FET comprising a first channel region, first and second source drains on opposite sides of the first channel region and a gate, the gate over the channel region and electrically isolated from the channel region by a first gate dielectric layer; and a FinFET formed in single crystal silicon block on top of and electrically isolated from the substrate, the FinFET comprising a second channel region, third and fourth source drains on opposite first and second ends of a second channel region and the gate, the gate electrically isolated from the second channel region by a second gate dielectric layer.
摘要翻译： 半导体器件。 该器件包括：形成在单晶硅衬底中的平面FET，所述FET包括第一沟道区，在第一沟道区的相对侧上的第一和第二源极漏极和栅极，沟道区上方的栅极和电隔离 从所述沟道区域通过第一栅极介电层; 以及在衬底顶部并与电极隔离的单晶硅块中形成的FinFET，所述FinFET包括第二沟道区，第三和第四源在第二沟道区的相对的第一和第二端上漏极，栅极电 通过第二栅极介电层与第二沟道区隔离。
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公开(公告)号：US20080090367A1
公开(公告)日：2008-04-17
申请号：US11549311
申请日：2006-10-13
IPC分类号： H01L21/336
CPC分类号： H01L29/42384 , H01L29/66772 , H01L29/78654
摘要： A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.
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公开(公告)号：US06512269B1
公开(公告)日：2003-01-28
申请号：US09657315
申请日：2000-09-07
申请人： Andres Bryant , Edward Joseph Nowak , Minh Ho Tong
发明人： Andres Bryant , Edward Joseph Nowak , Minh Ho Tong
IPC分类号： H01L2701
CPC分类号： H01L29/78696 , H01L21/84 , H01L27/1203 , H01L29/42384
摘要： A semiconductor device including an SOI substrate; a plurality of diffusion regions in substrate, separated by, and abutting a plurality of body regions in said substrate, a first one of the body regions and its abutting diffusion regions having a first width and successive ones of the body regions and their abutting diffusion regions having successively smaller widths; and a plurality of gates each over one of the plurality of body regions and separated from the body regions by a dielectric material, said plurality of gates connected to a common voltage terminal.
摘要翻译： 一种包括SOI衬底的半导体器件; 衬底中的多个扩散区域，分隔并邻接所述衬底中的多个主体区域，身体区域中的第一个和其邻接扩散区域具有第一宽度和连续的身体区域及其邻接扩散区域 具有相继较小的宽度; 以及多个栅极，每个栅极分别位于多个主体区域中的一个上，并且通过电介质材料与主体区域分离，所述多个栅极连接到公共电压端子。
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公开(公告)号：US06509725B1
公开(公告)日：2003-01-21
申请号：US09683025
申请日：2001-11-09
申请人： Kerry Bernstein , Peter Edwin Cottrell , Roger Paul Gregor , Stephen V. Kosonocky , Edward Joseph Nowak
发明人： Kerry Bernstein , Peter Edwin Cottrell , Roger Paul Gregor , Stephen V. Kosonocky , Edward Joseph Nowak
IPC分类号： G05F304
CPC分类号： G06F1/26
摘要： A system and method for achieving self-regulated voltage division among multiple serially stacked voltage planes. The system of the present invention is incorporated within a source voltage plane having a source supply node for supplying current and a source ground node for sinking current supplied therefrom. An intermediate voltage supply node is coupled between the source supply voltage node and the source ground node for dividing the source voltage plane into a plurality of intermediate voltage planes. The self-regulated voltage divider of the present invention includes a first capacitor and a second capacitor that are each controllably coupled between either the source supply voltage node and the intermediate voltage supply node, or between the intermediate voltage supply node and the source ground node, such that a voltage level balance is achieved among the intermediate voltage planes.
摘要翻译： 一种用于在多个串联电压平面之间实现自调节电压分配的系统和方法。 本发明的系统结合在具有用于提供电流的源电源节点的源极电压平面和用于吸收从其提供的电流的源极接地节点。 中间电压供应节点耦合在源电源电压节点和源极接地节点之间，用于将源极电压平面分成多个中间电压平面。 本发明的自调节分压器包括第一电容器和第二电容器，每个可控制地耦合在源电源电压节点和中间电压供应节点之间，或者在中间电压供应节点和源极接地节点之间， 使得在中间电压平面之间实现电压电平平衡。
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公开(公告)号：US06432754B1
公开(公告)日：2002-08-13
申请号：US09788979
申请日：2001-02-20
申请人： Fariborz Assaderaghi , Tze-Chiang Chen , K. Paul Muller , Edward Joseph Nowak , Devendra Kumar Sadana , Ghavam G. Shahidi
发明人： Fariborz Assaderaghi , Tze-Chiang Chen , K. Paul Muller , Edward Joseph Nowak , Devendra Kumar Sadana , Ghavam G. Shahidi
IPC分类号： H01L2100
CPC分类号： H01L29/78696 , H01L29/41733 , H01L29/66772 , H01L29/78603 , H01L29/78618
摘要： The present invention provides various methods for forming a ground-plane SOI device which comprises at least a field effect transistor formed on a top Si-containing surface of a silicon-on-insulator (SOI) wafer; and an oxide region present beneath the field effect transistor, located in an area between source and drain regions which are formed in said SOI wafer, said oxide region is butted against shallow extensions formed in said SOI wafer, and is laterally adjacent to said source and drain regions.
摘要翻译： 本发明提供了用于形成接地平面SOI器件的各种方法，该器件至少包括形成在绝缘体上硅（SOI）晶片的顶部含Si表面上的场效应晶体管; 以及位于场效应晶体管下方的氧化物区域，位于形成在所述SOI晶片中的源极和漏极区域之间的区域中，所述氧化物区域与所述SOI晶片中形成的浅延伸区对接，并且与所述源极侧向相邻， 漏区。
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公开(公告)号：US06429056B1
公开(公告)日：2002-08-06
申请号：US09447122
申请日：1999-11-22
IPC分类号： H01L2184
CPC分类号： H01L21/84 , H01L29/78609 , H01L29/78612
摘要： Described is a dynamic threshold field effect transistor (DTFET) that includes a gate-to-body contact structure within the gate. By forming the gate-to-body contact structure that can reduce the gate-to-body contact resistance and increase the device packing density, the DTFET can be used in silicon on insulator (SOI) technologies and take full advantages of the DT-CMOS performance benefit.
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