公开(公告)号：US5574921A

公开(公告)日：1996-11-12

申请号：US468484

申请日：1995-06-06

申请人： Brian W. Curran

发明人： Brian W. Curran

IPC分类号： G06F13/40 ,  G06F1/32

CPC分类号： G06F13/4072 ,  Y02B60/1228 ,  Y02B60/1235

摘要： In a computer system comprising a plurality of subsystems, interconnected by a bus comprising bit drivers and bit receivers, data words are transmitted on the bus in the form of code words. The code words are formulated such that the number of bits of the bus which changes with the transmission of successive code words is minimized. A switching code, comprising one or more bits, defines a plurality of napping codes and a data word to be transmitted is mapped by use of the mapping codes to a plurality of code words. One of the plurality of code words differing from a previously transmitted code word in the least number of bit positions is selected. The selected code words is transmitted, together with a switching code, identifying the mapping from which the transmitted code word was generated. At the receiving end of the bus, the switching code is decoded to identify the mapping used in creating the code word. Using the identified mapping, the original data word is recovered.

摘要翻译： 在包括由包括位驱动器和位接收器的总线互连的多个子系统的计算机系统中，数据字以代码字的形式在总线上传送。 编码字被配置为使得随着连续代码字的传输而变化的总线的位数最小化。 包括一个或多个位的切换代码定义多个起跳代码，并且将要发送的数据字通过使用映射代码映射到多个代码字。 选择与最少数量的位位置中的先前发送的代码字不同的多个代码字中的一个。 所选择的代码字与切换代码一起发送，识别生成发送的代码字的映射。 在总线的接收端，对切换代码进行解码以识别用于创建代码字的映射。 使用识别的映射，恢复原始数据字。

公开(公告)号：US5554946A

公开(公告)日：1996-09-10

申请号：US224927

申请日：1994-04-08

申请人： Brian W. Curran ,  Rafael Blanco

发明人： Brian W. Curran ,  Rafael Blanco

IPC分类号： G11C7/10 ,  G11C7/22 ,  H03K5/13

CPC分类号： G11C7/22 ,  G11C7/1072 ,  H03K5/131 ,  H03K5/133

摘要： A programmable, timing signal generator propagates a digital wave along a delay chain comprised of series connected inverters that has sufficient stages that the edge of the wave will not propagate to the end during one system clock cycle time. The delay chain is sampled once each clock cycle, and the point to which the wave has progressed is encoded. Programmable, fine leading and fine trailing edge registers store, as a fraction of the clock cycle time, the desired locations of the timing signal leading and trailing edge relative to the clock edges.

摘要翻译： 可编程的定时信号发生器沿着包括串联连接的反相器的延迟链传播数字波，其具有足够的级，使得在一个系统时钟周期期间波的边缘将不会传播到结束。 每个时钟周期对延迟链进行采样，并对波进行的点进行编码。 可编程，精细的前沿和精细的后沿寄存器作为时钟周期时间的一小部分存储定时信号前沿和后沿相对于时钟边沿的期望位置。

公开(公告)号：US5939915A

公开(公告)日：1999-08-17

申请号：US907346

申请日：1997-08-06

申请人： Brian W. Curran

发明人： Brian W. Curran

IPC分类号： H03K3/013 ,  H03K3/037 ,  H03K3/356 ,  H03K3/289

CPC分类号： H03K3/037 ,  H03K3/013 ,  H03K3/356156

摘要： A non-buffered, noise-immune transmission gate latch for high performance applications is disclosed. The latch data input circuit contains an additional PFET for pulling up the gate of a transmission PFET and an additional NFET to pull down the gate of the transmission NFET to prevent the transmission gate from inadvertently opening when noise is coupled into the data input node. When data input voltage rises to Vdd+Vtp, the additional PFET begins to turn ON, and an inverted clock node is pulled above Vdd. The higher inverted clock node voltage is coupled to the gate of the transmission PFET and thereby prevents the transmission PFET from inadvertently turning ON. When data input voltage drops to -Vtn, the additional NFET begins to turn ON, and a clock node Is pulled below ground. The lower clock node voltage is coupled to the gate of the transmission NFET and thereby prevents the transmission NFET from inadvertently turning ON. Thus two additional transistors provide the necessary noise immunity.

摘要翻译： 公开了一种用于高性能应用的非缓冲，无噪声的传输门锁。 锁存数据输入电路包含用于提升传输PFET的栅极和附加NFET的附加PFET，以将传输NFET的栅极拉下来，以防止当噪声耦合到数据输入节点时传输门不经意地打开。 当数据输入电压上升到Vdd + Vtp时，附加PFET开始导通，反相时钟节点被拉到Vdd以上。 较高的反相时钟节点电压耦合到传输PFET的栅极，从而防止传输PFET无意中导通。 当数据输入电压下降到-Vtn时，额外的NFET开始导通，时钟节点被拉到地下。 较低时钟节点电压耦合到传输NFET的栅极，从而防止透射NFET无意中导通。 因此两个额外的晶体管提供必要的抗干扰能力。

公开(公告)号：US5568075A

公开(公告)日：1996-10-22

申请号：US453587

申请日：1995-05-30

申请人： Brian W. Curran ,  Rafael Blanco

发明人： Brian W. Curran ,  Rafael Blanco

IPC分类号： G11C7/10 ,  G11C7/22 ,  H03K5/13

CPC分类号： G11C7/22 ,  G11C7/1072 ,  H03K5/131 ,  H03K5/133

摘要： A programmable, timing signal generator propagates a digital wave along a delay chain comprised of series connected inverters that has sufficient stages that the edge of the wave will not propagate to the end during one system clock cycle time. The delay chain is sampled once each clock cycle, and the point to which the wave has progressed is encoded. Programmable, fine leading and fine trailing edge registers store, as a fraction of the clock cycle time, the desired locations of the timing signal leading and trailing edge relative to the clock edges.

公开(公告)号：US06816824B2

公开(公告)日：2004-11-09

申请号：US09294178

申请日：1999-04-19

申请人： Ching-Te K. Chuang ,  Brian W. Curran ,  George E. Smith, III

发明人： Ching-Te K. Chuang ,  Brian W. Curran ,  George E. Smith, III

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： Low-conductance and high-conductance IV characteristics (models) are created using the low and high end of their body voltage ranges, respectively. The body voltage of the device (FET) is initialized to the low end of range at time zero, and then a transient, two dimensional sweep of gate and drain voltages is performed. Drain currents are measured in this two dimensional region and are used to create a piecewise, linear IV model of device. The process is repeated for the highest body voltage. This process differs significantly from prior art bulk device characterization techniques, which did not have to initialize body voltage or perform a transient analysis. The body voltage is modulating during the switching event due to the gate-to-body and diffusion-to-body coupling; and thus only a transient analysis can properly model these coupling effects.

公开(公告)号：US06768365B2

公开(公告)日：2004-07-27

申请号：US10274191

申请日：2002-10-18

申请人： Brian W. Curran ,  Edward T. Malley

发明人： Brian W. Curran ,  Edward T. Malley

IPC分类号： G06F104

CPC分类号： G06F1/32 ,  G06F1/04

摘要： An improved clocking circuit is provided for generating a half swing clock. Previous circuit operations required an additional supply voltage rail (Vdd/2), but the preferred embodiment exploits charge sharing to generate a half swing clock with less power and without the additional supply voltage rail. To drive clock nodes to Vdd/2, a shunt transistor is opened, and the fully charged clock node shares its charge with the fully discharged clock node. When capacitances have been properly matched, both nodes will settle at Vdd/2.

摘要翻译： 提供改进的时钟电路用于产生半摆时钟。 以前的电路操作需要额外的电源电压轨（Vdd / 2），但是优选实施例利用电荷共享来产生具有较少功率的半摆动时钟，而不需要额外的电源电压轨。 为了将时钟节点驱动到Vdd / 2，分路晶体管断开，完全充电的时钟节点与完全放电的时钟节点共享其电荷。 当电容正确匹配时，两个节点都将以Vdd / 2的速度进行定位。

公开(公告)号：US06661262B1

公开(公告)日：2003-12-09

申请号：US10177323

申请日：2002-06-20

申请人： Brian W. Curran

发明人： Brian W. Curran

IPC分类号： H03B1900

CPC分类号： H03K5/151 ,  H03K5/00006

摘要： A clock generation circuit globally distributes a half-frequency clock and doubles the clock frequency locally in a local clock block circuit. The circuit contains several subcircuits which detect the global clock edges (transitions), double the clock frequency and generate two shaped local clocks. A rising edge detection circuit generates a pulse in response to a rising edge of the global clock. A falling edge detection circuit generates a pulse in response to a falling edge of the global clock. A master clock SR (set/reset) latch is reset in response to either pulse and a slave clock SR latch is set in response to either pulse. A delay circuit generates a delayed signal in response to the setting of the master clock SR latch. This delayed signal sets the master clock SR latch and resets the slave clock SR latch. The master clock latch output is repowered to drive the master latches and the slave clock latch output is repowered to drive the slave latches.

摘要翻译： 时钟发生电路全局分配半频时钟，并在本地时钟块电路中本地将时钟频率加倍。 该电路包含几个检测全局时钟边沿（转换）的子电路，是时钟频率的两倍，并产生两个本地时钟。 上升沿检测电路响应于全局时钟的上升沿产生脉冲。 下降沿检测电路响应于全局时钟的下降沿产生脉冲。 主时钟SR（置位/复位）锁存器响应于任一脉冲被复位，并且从时钟SR锁存器被设置为响应于任一脉冲。 延迟电路响应于主时钟SR锁存器的设置而产生延迟的信号。 该延迟信号设置主时钟SR锁存器并复位从时钟SR锁存器。 主时钟锁存器输出被驱动以驱动主锁存器，从时钟锁存器输出被驱动以驱动从锁存器。

公开(公告)号：US06657471B1

公开(公告)日：2003-12-02

申请号：US10290649

申请日：2002-11-08

申请人： Brian W. Curran ,  Edward T. Malley

发明人： Brian W. Curran ,  Edward T. Malley

IPC分类号： G11C706

CPC分类号： H03K3/012 ,  H03K3/356139 ,  H03K3/356182

摘要： An improved pull-down latch circuit is provided for better latch performance. Previous pull-down latch circuit performance is compromised during pull-up operation since weak PFETs are employed to pull up latch nodes. A pull up assist circuit is incorporated to assist weak PFET when latch node is being pulled up. The assist circuit is isolated from latch circuit when latch node is being pull down to guarantee that pull down circuit can overcome pull-up circuit (for correct latch operation).

摘要翻译： 提供了一种改进的下拉锁存电路，用于更好的锁存性能。 在上拉操作期间，先前的下拉锁存电路性能受损，因为采用弱PFET来上拉锁存器节点。 当上拉闩锁节点时，引入一个上拉辅助电路来辅助弱PFET。 当锁存节点被拉下时，辅助电路与锁存电路隔离，以保证下拉电路可以克服上拉电路（用于正确的锁存器操作）。

公开(公告)号：US06426661B1

公开(公告)日：2002-07-30

申请号：US09933193

申请日：2001-08-20

申请人： Brian W. Curran

发明人： Brian W. Curran

IPC分类号： G11C514

CPC分类号： H03K19/00384 ,  G06F1/10 ,  H03K5/133 ,  H03K19/00323 ,  H03K2005/00039 ,  H03K2005/0013

摘要： A voltage-compensated, constant delay clock buffer for a chip clock distribution circuit employs a variable gain circuit to dynamically control the delay through the first inverter stage. In the presence of no voltage rail collapse the first stage gain is set high which results in a nominal delay through the first stage. As voltage rail collapse occurs local to the clock buffer circuit, the gain on the first stage is reduced to yield a smaller than nominal delay through the first stage in such a way as to compensate for the increased delay in the subsequent stage or stages. The control circuit is responsive to a first voltage rail and a second voltage rail to provide dynamic control of the delay through the first inverter stage. The circuit can compensate the circuit to handle a plurality of second inverter stages with the control circuit adjusting the delay of said first inverter stage, and with the control circuit remaining responsive to a first voltage rail and a second voltage rail.

摘要翻译： 用于芯片时钟分配电路的经电压补偿的恒定延迟时钟缓冲器采用可变增益电路来动态地控制通过第一反相器级的延迟。 在没有电压轨道崩溃的情况下，第一级增益被设置为高，这导致通过第一级的标称延迟。 当时钟缓冲器电路局部出现电压塌陷时，第一级的增益减小，从而产生比第一级小的额定延迟，以便补偿后续级或级的增加的延迟。 控制电路响应于第一电压轨和第二电压轨，以提供通过第一逆变器级的延迟的动态控制。 电路可以补偿电路来处理多个第二逆变器级，其中控制电路调节所述第一逆变器级的延迟，并且控制电路对第一电压轨和第二电压轨保持响应。

公开(公告)号：US5278967A

公开(公告)日：1994-01-11

申请号：US576252

申请日：1990-08-31

申请人： Brian W. Curran

发明人： Brian W. Curran

IPC分类号： G06F12/06 ,  G06F12/02 ,  G11C11/401

CPC分类号： G06F12/0215

摘要： A programmable memory controller generates address and control signal information associated with a word of data which is desired to be transferred first from dynamic random access memory (DRAM) modules. The generated information specifically assists memory support circuitry interfacing with page mode DRAMs. This information is normally provided to the memory support circuitry just before selection of the staring word from a fetch line data buffer. Memory latency, gaps in data transfer, can be reduced when this information is available to the support circuitry as it drives column address and/or column address strobe (CAS) signals to the DRAMs.

摘要翻译： 可编程存储器控制器产生与期望首先从动态随机存取存储器（DRAM）模块传送的数据字相关联的地址和控制信号信息。 所产生的信息具体协助与页面模式DRAM接口的存储器支持电路。 该信息通常在从取出行数据缓冲器选择起始字之前提供给存储器支持电路。 当信息可用于支持电路时，当驱动列地址和/或列地址选通（CAS）信号到DRAM时，可以减少存储器延迟，数据传输中的间隙。