公开(公告)号：US10777680B2

公开(公告)日：2020-09-15

申请号：US16534557

申请日：2019-08-07

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Remy Berthelon ,  Francois Andrieu

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L21/762 ,  H01L27/02 ,  H01L29/786 ,  H01L27/092

Abstract: Longitudinal trenches extend between and on either side of first and second side-by-side strip areas. Transverse trenches extend from one edge to another edge of the first strip area to define tensilely strained semiconductor slabs in the first strip area, with the second strip area including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip area, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip area, P-channel MOS transistors are located inside and on top of the portions.

公开(公告)号：US10651202B2

公开(公告)日：2020-05-12

申请号：US16196390

申请日：2018-11-20

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Francois Andrieu ,  Perrine Batude ,  Maud Vinet

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L23/528 ,  H01L23/522 ,  H01L27/06 ,  H01L21/822 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/532 ,  H01L21/033 ,  H01L21/768 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092

Abstract: An integrated circuit is provided with several superimposed levels of transistors, the circuit including an upper level provided with transistors having a rear gate electrode laid out on a first semiconducting layer, and a second semiconducting layer, a first transistor among the transistors of the upper level being provided with a contact pad traversing the second semiconducting layer, the contact pad being connected to a connection zone disposed between the first semiconducting layer and the second semiconducting layer, the first transistor being polarised by and connected to at least one power supply line disposed on a side of a front face of the second semiconducting layer that is opposite to the rear face.

公开(公告)号：US09876032B2

公开(公告)日：2018-01-23

申请号：US15296205

申请日：2016-10-18

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Sonarith Chhun ,  Emmanuel Josse ,  Gregory Bidal ,  Dominique Golanski ,  Francois Andrieu ,  Jerome Mazurier ,  Olivier Weber

IPC: H01L21/336 ,  H01L27/092 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/84 ,  H01L21/02 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L27/1203 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30608 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/41783 ,  H01L29/6653

Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.

公开(公告)号：US20170194498A1

公开(公告)日：2017-07-06

申请号：US15387712

申请日：2016-12-22

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Remy Berthelon ,  Didier Dutartre ,  Pierre Morin ,  Francois Andrieu ,  Elise Baylac

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7849 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/76281 ,  H01L21/76283 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/78684

Abstract: A strained semiconductor layer is produced from a semiconductor layer extending on an insulating layer. A thermal oxidization is performed on the semiconductor layer across its entire thickness to form two bars extending in a direction of a transistor width. Insulating trenches are formed in a direction of a transistor length. A strain of the strained semiconductor layer is induced in one implementation before the thermal oxidation is performed. Alternatively, the strain is induced after the thermal oxidation is performed. The insulating trenches serve to release a component of the strain extending in the direction of transistor width. A component of the strain extending in the direction of transistor length is maintained. The bars and trenches delimit an active area of the transistor include source, drain and channel regions.

公开(公告)号：US09514996B2

公开(公告)日：2016-12-06

申请号：US15099892

申请日：2016-04-15

Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives

Inventor： Francois Andrieu ,  Denis Rideau

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/06 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L21/84 ,  H01L21/30604 ,  H01L21/762 ,  H01L21/76283 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66621 ,  H01L29/7846 ,  H01L29/78618 ,  H01L29/78684

Abstract: A process for fabricating field-effect transistors, including providing a first semiconductor band surmounted with a first semiconductor layer; providing a second semiconductor band surmounted with a second semiconductor layer; providing a buried insulating layer; providing a deep trench isolation passing through the buried insulating layer and isolating the first semiconductor band from the second semiconductor band; etching the first semiconductor band so as to form a first row of semiconductor islands; etching the second semiconductor band so as to form a second row of semiconductor islands; and forming sacrificial gates on the first semiconductor layer and on the second semiconductor layer.

Abstract translation: 一种用于制造场效应晶体管的工艺，包括提供一个覆盖有第一半导体层的第一半导体带; 提供了具有第二半导体层的第二半导体带; 提供掩埋绝缘层; 提供通过所述掩埋绝缘层并将所述第一半导体带与所述第二半导体带隔离的深沟槽隔离; 蚀刻第一半导体带以形成第一行半导体岛; 蚀刻第二半导体带以形成第二行半导体岛; 以及在所述第一半导体层上和所述第二半导体层上形成牺牲栅极。

公开(公告)号：US20160099183A1

公开(公告)日：2016-04-07

申请号：US14965990

申请日：2015-12-11

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Denis Rideau ,  Elise Baylac ,  Emmanuel Richard ,  Francois Andrieu

IPC: H01L21/84 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/10

CPC classification number: H01L21/84 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/1218 ,  H01L27/1262 ,  H01L27/127 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78603

Abstract: The transverse mechanical stress within the active region of a MOS transistor is relaxed by forming an insulating incursion, such as an insulated trench, within the active region of the MOS transistor. The insulated incursion is provided at least in a channel region of the MOS transistor so as to separate the channel region into two parts. The insulated incursion is configured to extend in a direction of a length of the MOS transistor. The insulated incursion may further extend into one or more of a source region or drain region located adjacent the channel region of the MOS transistor.

公开(公告)号：US11011425B2

公开(公告)日：2021-05-18

申请号：US16525043

申请日：2019-07-29

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Perrine Batude ,  Francois Andrieu ,  Maud Vinet

IPC: H01L21/822 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/265 ,  H01L21/225

Abstract: A method of production of a 3D microelectronic device includes assembling a structure comprising a lower level with a component partially formed in a first semiconductor layer with a support provided with a second semiconductor layer in which a transistor channel of an upper level is capable of being produced, the second semiconductor layer being capped with a dielectric material layer capable of forming a gate dielectric, forming a capping layer arranged on the dielectric material layer, and potentially capable of forming a lower gate portion of the transistor, and defining a gate dielectric zone and an active zone of said transistor by etching the dielectric material layer and the second semiconductor layer, the capping layer protecting said dielectric material layer during this etching.

公开(公告)号：US10446548B2

公开(公告)日：2019-10-15

申请号：US15706952

申请日：2017-09-18

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Francois Andrieu ,  Remy Berthelon

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/10 ,  H01L27/02

Abstract: An integrated circuit is provided, including: a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and the second nMOS transistors including a channel region made of silicon that is subjected to tensile stress, and their respective gates being positioned at least 250 nm from a border of their active zone; and a third pair including a third nMOS transistor having a same construction as the second nMOS transistor and a third pMOS transistor having a same construction as the first pMOS transistor and having a tensile stress that is lower by at least 250 MPa than the tensile stress of the channel region, respective gates of the transistors of the third pair being positioned at most 200 nm from a border of their active zone.

公开(公告)号：US10263110B2

公开(公告)日：2019-04-16

申请号：US15387712

申请日：2016-12-22

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Remy Berthelon ,  Didier Dutartre ,  Pierre Morin ,  Francois Andrieu ,  Elise Baylac

IPC: H01L29/207 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

Abstract: A strained semiconductor layer is produced from a semiconductor layer extending on an insulating layer. A thermal oxidization is performed on the semiconductor layer across its entire thickness to form two bars extending in a direction of a transistor width. Insulating trenches are formed in a direction of a transistor length. A strain of the strained semiconductor layer is induced in one implementation before the thermal oxidation is performed. Alternatively, the strain is induced after the thermal oxidation is performed. The insulating trenches serve to release a component of the strain extending in the direction of transistor width. A component of the strain extending in the direction of transistor length is maintained. The bars and trenches delimit an active area of the transistor include source, drain and channel regions.

公开(公告)号：US20170117296A1

公开(公告)日：2017-04-27

申请号：US15296205

申请日：2016-10-18

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Sonarith Chhun ,  Emmanuel Josse ,  Gregory Bidal ,  Dominique Golanski ,  Francois Andrieu ,  Jerome Mazurier ,  Olivier Weber

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30608 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/41783 ,  H01L29/6653

Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.