公开(公告)号：US20200336076A1

公开(公告)日：2020-10-22

申请号：US16959116

申请日：2018-12-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. ,  SOUTHEAST UNIVERSITY

Inventor： Qinsong QIAN ,  Shengyou XU ,  Feng LIN ,  Hao WANG ,  Wei SU ,  Qi LIU ,  Longxing SHI

IPC: H02M3/335

Abstract: A control system for synchronous rectifying transistor of LLC converter, the system comprising a voltage sampling circuit, a high-pass filtering circuit, a PI compensation and effective value detection circuit, and a control system taking a microcontroller (MCU) as a core. When the LLC converter is operating at a high frequency, a drain-source voltage VDS(SR) of the synchronous rectifying transistor delivers, via the sampling circuit, a change signal of the drain-source voltage during turn-off into the high-pass filtering circuit and the PI compensation and effective value detection circuit to obtain an effective value amplification signal of a drain-source voltage oscillation signal caused by parasitic parameters, and the current value is compared with a previously collected value via a control circuit taking a microcontroller (MCU) as a core, so as to change a turning-on time of the synchronous rectifying transistor in the next period.

公开(公告)号：US20180262186A1

公开(公告)日：2018-09-13

申请号：US15779432

申请日：2017-01-23

Applicant: SOUTHEAST UNIVERSITY ,  SOUTHEAST UNIVERSITY-WUXI INTEGRATED CIRCUIT TECHNOLOGY RESEARCH INSTITUTE

Inventor： Weifeng SUN ,  Yunwu ZHANG ,  Kuo YU ,  Jing ZHU ,  Shen XU ,  Qinsong QIAN ,  Siyang LIU ,  Shengli LU ,  Longxing SHI

IPC: H03K17/06 ,  H03K17/687 ,  H03K17/16

CPC classification number: H03K17/063 ,  H01L27/0727 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/7835 ,  H03K17/162 ,  H03K17/6871 ,  H03K19/0185 ,  H03K2217/0063 ,  H03K2217/0081

Abstract: Parasitic high-voltage diodes implemented by integration technology in a high-voltage level shift circuit are used for charging a bootstrap capacitor CB, wherein a power supply end of the high voltage level shift circuit is a high-side floating power supply VB, and a reference ground is a floating voltage PGD that is controlled by a bootstrap control circuit. A first parasitic diode DB1 and a second parasitic diode DB2 are provided between the VB and the PGD. The bootstrap control circuit is controlled by a high-side signal and a low-side signal.

公开(公告)号：US20250085315A1

公开(公告)日：2025-03-13

申请号：US18567382

申请日：2022-12-29

Applicant: SOUTHEAST UNIVERSITY

Inventor： Qinsong QIAN ,  Song DING ,  Chunyan NIE ,  Yuanhang ZHOU ,  Weifeng SUN ,  Longxing SHI

IPC: G01R19/00 ,  H02M1/00 ,  H02M3/335

Abstract: A lossless exciting current sampling circuit for an isolated converter includes first and second voltage sampling circuits and a subtraction circuit formed by an operational amplifier. The two sampling circuits sample voltages of the primary winding of an isolation transformer, with outputs fed into the subtracter. The subtracter output is the circuit's output. RC low-pass filters with large time constants are used as primary voltage sampling circuits, realizing integration of voltage differences between the exciting inductance terminals, enabling lossless current sampling without resistors or transformers. The current sampling result is utilized for volt-second balance control, realized along with a hold circuit and comparator which compares the sampling hold result with the current sampling result to generate a control signal.

公开(公告)号：US20240266430A1

公开(公告)日：2024-08-08

申请号：US18577714

申请日：2022-12-29

Applicant: SOUTHEAST UNIVERSITY

Inventor： Long ZHANG ,  Weifeng SUN ,  Siyang LIU ,  Jie MA ,  Peigang LIU ,  Longxing SHI

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/20 ,  H01L29/207

CPC classification number: H01L29/7787 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/207

Abstract: An enhancement-mode N-channel and P-channel GaN device integration structure comprises a substrate, wherein an Al—N nucleating layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer are sequentially arranged on the substrate, and the AlGaN barrier layer and the GaN channel layer are divided by an isolation layer; a P-channel device is arranged on one side of the isolation layer and comprises a first P-GaN layer, a first GaN isolation layer and a first P+-GaN layer are sequentially arranged on the first P-GaN layer, a first source, a first gate and a first drain are arranged on the first P+-GaN layer, the first gate is inlaid in the first P+-GaN layer, and a gate dielectric layer is arranged between the first gate and the first P+-GaN layer; and an N-channel device is arranged on the other side of the isolation layer.

公开(公告)号：US20240266959A1

公开(公告)日：2024-08-08

申请号：US18566102

申请日：2022-09-26

Applicant: SOUTHEAST UNIVERSITY

Inventor： Qi LIU ,  Weiwei ZHAI ,  Leilei SHI ,  Qinsong QIAN ,  Weifeng SUN ,  Longxing SHI

IPC: H02M3/158 ,  H02M1/00 ,  H02M1/088

CPC classification number: H02M3/1582 ,  H02M1/0058 ,  H02M1/088

Abstract: A control method for a four-switch buck-boost converter is provided. The control method adopts four-stage control, and divides the load range into two sections and adopts different control strategies according to a critical load value corresponding to optimal control. In Boost mode, before the critical load, T1 and T2 are kept constant, T3 is a minimum value for realizing soft-switching, and T4 decreases with the increase of the load; when the critical load is reached, T4 drops to 0; and after the critical load, T1, T2, T3 and T increase with the load. In Buck mode, before the critical load, T2 and T3 are kept constant, T1 is a minimum value for realizing soft-switching, and T4 decreases with the increase of the load; when the critical load is reached, T4 drops to 0; and after the critical load, T1, T2, T3 and T increase with the load.

公开(公告)号：US20210194375A1

公开(公告)日：2021-06-24

申请号：US16617508

申请日：2018-09-28

Applicant: SOUTHEAST UNIVERSITY

Inventor： Qinsong QIAN ,  Shengyou XU ,  Qi LIU ,  Weifeng SUN ,  Shengli LU ,  Longxing SHI

IPC: H02M3/335 ,  H02M1/08

Abstract: The invention discloses a self-adaptive synchronous rectification control system and a self-adaptive synchronous rectification control method of an active clamp flyback converter. The control system comprises a sampling and signal processing circuit, a control circuit with a microcontroller as a core and a gate driver. According to the control method, a switching-on state, an early switching-off state, a late switching-off state and an exact switching-off state of a secondary synchronous rectifier of the active clamp flyback converter can be directly detected, and the synchronous rectifier and a switching-on time of the synchronous rectifier in next cycle can be controlled according to a detection result. After several cycles of self-adaptive control, the synchronous rectifier enters the exact switching-on state, thus avoiding oscillation of an output waveform of the active clamp flyback converter.

公开(公告)号：US20200342295A1

公开(公告)日：2020-10-29

申请号：US16757421

申请日：2019-01-24

Applicant: Southeast University

Inventor： Bo LIU ,  Yu GONG ,  Wei GE ,  Jun YANG ,  Longxing SHI

IPC: G06N3/063 ,  G06N3/08 ,  G06F7/544 ,  G06F7/523 ,  G06F7/50

Abstract: The present invention relates to the field of analog integrated circuits, and provides a multiply-accumulate calculation method and circuit suitable for a neural network, which realizes large-scale multiply-accumulate calculation of the neural network with low power consumption and high speed. The multiply-accumulate calculation circuit comprises a multiplication calculation circuit array and an accumulation calculation circuit. The multiplication calculation circuit array is composed of M groups of multiplication calculation circuits. Each group of multiplication calculation circuits is composed of one multiplication array unit and eight selection-shift units. The order of the multiplication array unit is quantized in real time by using on-chip training to provide a shared input for the selection-shift units, achieving increased operating rate and reduced power consumption. The accumulation calculation circuit is composed of a delay accumulation circuit, a TDC conversion circuit, and a shift-addition circuit in series. The delay accumulation circuit comprises eight controllable delay chains for dynamically controlling the number of iterations and accumulating data multiple times in a time domain, so as to meet the difference in calculation scale of different network layers, save hardware storage space, reduce calculation complexity, and reduce data scheduling.

公开(公告)号：US20210234030A1

公开(公告)日：2021-07-29

申请号：US16969437

申请日：2019-10-21

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng SUN ,  Siyang LIU ,  Sheng LI ,  Chi ZHANG ,  Xinyi TAO ,  Ningbo LI ,  Longxing SHI

IPC: H01L29/778

Abstract: A heterojunction semiconductor device comprises a substrate; a second barrier layer is disposed on the second channel layer and a second channel is formed; a trench gate structure is disposed in the second barrier layer; the trench gate structure is embedded into the second barrier layer and is composed of a gate medium and a gate metal located in the gate medium; an isolation layer is disposed in the second channel layer and separates the second channel layer into an upper layer and a lower layer; a first barrier layer is disposed between the lower layer of the second channel layer and the first channel layer and a first channel is formed; a bottom of the metal drain is flush with a bottom of the first barrier layer; and a first metal source is disposed between the second metal source and the first channel layer.

公开(公告)号：US20210218396A1

公开(公告)日：2021-07-15

申请号：US17044623

申请日：2020-04-15

Applicant: SOUTHEAST UNIVERSITY

Inventor： Jing ZHU ,  Weifeng SUN ,  Bowei YANG ,  Siyuan YU ,  Yangyang LU ,  Longxing SHI ,  Shengli LU

IPC: H03K17/687 ,  H03K19/20

Abstract: The present invention discloses a gate drive circuit for reducing a reverse recovery current of a power device, and belongs to the field of basic electronic circuit technologies. The gate drive circuit includes a high-voltage LDMOS transistor, a diode forming a freewheeling path when the diode is turned on or a low-voltage MOS transistor in anti-parallel connection with a body diode, and a voltage detection circuit. When the power device is turned off, a freewheeling current produced by an inductive load flows through a freewheeling diode, the voltage detection circuit detects that the freewheeling diode is turned on, and an output signal is processed by a control circuit, to cause the drive circuit to output a high level, so that channels of the power device and the high-voltage LDMOS transistor are turned on, the freewheeling current flows through the conductive channels, almost not through the freewheeling diode, and there is no reverse recovery current in the freewheeling diode at this time, thereby reducing the reverse recovery current of the power device.

公开(公告)号：US20180253521A1

公开(公告)日：2018-09-06

申请号：US15560161

申请日：2017-02-24

Applicant: Southeast University

Inventor： Weiwei SHAN ,  Wentao DAI ,  Jun YANG ,  Longxing SHI

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5031 ,  G06F2217/84 ,  H03K5/1534 ,  H03K5/19

Abstract: An online monitoring unit and a control circuit for ultra-wide voltage range applications are disclosed. Compared with a conventional online monitoring unit, the present invention eliminates the need to reserve delay units, replaces flip-flops in the conventional online monitoring unit with a latch, and uses a transition detector with fewer transistors than that of a shadow latch in the conventional online monitoring unit, thereby reducing the area and the power consumption of the online monitoring unit significantly and improving the energy efficiency of online monitoring techniques. In addition, in the ultra-wide voltage range applications, the time borrowing property of the latch adopted by the present invention can be utilized to prevent a timing error caused by PVT variations, thus enabling the minimization of timing margin and ensuring higher power efficiency. The present invention also discloses a control circuit for use with the online monitoring unit.