公开(公告)号：US12205673B1

公开(公告)日：2025-01-21

申请号：US17945902

申请日：2022-09-15

Applicant: Cadence Design Systems, Inc.

Inventor： Hari Anand Ravi ,  Sachin Ramesh Gugwad ,  Jitendra Kumar Yadav ,  Thomas Evan Wilson ,  Vinod Kumar

IPC: G11C8/18 ,  G06F1/12 ,  G06F13/20 ,  G11C7/22

Abstract: Various embodiments described herein provide for a read data strobe (RDQS) path having variation compensation (e.g., voltage and temperature compensation), delay lines, or both, where the RDQS path can be included by a physical (PHY) interface for a memory device, such as a Double Data Rate (DDR) Dynamic Random-Access Memory (DRAM) memory device.

公开(公告)号：US09997214B1

公开(公告)日：2018-06-12

申请号：US15637711

申请日：2017-06-29

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar ,  Tara Vishin

IPC: G11C7/00 ,  G11C7/10 ,  G11C14/00 ,  G11C5/14 ,  G11C11/40 ,  H03K19/173 ,  H03K19/00 ,  H03K19/0185

CPC classification number: G11C7/1057 ,  G11C5/145 ,  G11C5/147 ,  G11C7/1069 ,  G11C11/40 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4096 ,  G11C14/0009 ,  G11C2207/105 ,  H03K19/00 ,  H03K19/0005 ,  H03K19/0185 ,  H03K19/018521 ,  H03K19/173 ,  H03K19/1733

Abstract: Disclosed is an architecture for an output driver that does not employ level shifters in the high speed data path. Since the proposed architecture is free from level shifters in the high speed data path, it provides better performance across PVT corners. The disclosed output driver usages a hybrid pullup driver which makes it compatible for the wide range of DRAM supply range. This approach allows for significant savings for electronic design area and dynamic power.

公开(公告)号：US11323296B1

公开(公告)日：2022-05-03

申请号：US16943535

申请日：2020-07-30

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Sachin Ramesh Gugwad ,  Hari Anand Ravi ,  Thomas E Wilson ,  Vinod Kumar

IPC: H04L25/03 ,  H04L27/01

Abstract: The embodiments described herein provide for a method and system for training an optimal decision feedback equalization (DFE) coefficient for use in GDDR and DDR applications. The method includes determining a first expected bit pattern using a reference voltage. The method further includes determining a transition voltage value of the first expected bit pattern. The method further includes receiving a second expected bit pattern having a same first bit as the first expected bit pattern. The method further includes determining a transition voltage value of the second expected bit pattern using the reference voltage. The method further includes calculating an optimal reference voltage value by averaging the transition voltage values of the first expected bit pattern and the second-expected bit pattern and storing the optimal reference voltage value in a register corresponding to a logic value of the same first bit.

公开(公告)号：US11082267B1

公开(公告)日：2021-08-03

申请号：US16904019

申请日：2020-06-17

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Vinod Kumar ,  Harsh Anil Shakrani ,  Balbeer Rathor

IPC: H04L25/03 ,  G11C7/10

Abstract: The embodiments described herein provide for a method and system for implementing a multi-tap hybrid-equalization technique devoid of ISI jitter and PSI jitter in the high-speed data path to achieve 24 Gbps operating speed in systems utilizing GDDR6 DRAM. The method includes receiving an original data signal at a first TFFE circuit and receiving an altered data signal at a second TFFE circuit. The method further comprises generating a time-domain-equalized original data signal using a set of TFFE coefficients from the original data signal. The method further comprises generating a time-domain-equalized altered data signal using the set of TFFE coefficients from the altered data signal. The method further comprises generating, a time-and-voltage-domain-equalized data signal from the time-domain-equalized original data signal and the time-domain-equalized altered data signal at a voltage-feed forward equalization (VFFE) circuit using a set of VFFE coefficients.

公开(公告)号：US10536147B1

公开(公告)日：2020-01-14

申请号：US15635886

申请日：2017-06-28

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar ,  Karishma

IPC: H03K19/0185 ,  G11C11/407

Abstract: The present disclosure relates to an apparatus including level shifter circuitry configured to convert a voltage between one or more multi-voltage domains. The apparatus may include an integrated circuit having a cross-coupled latch including a first weak transistor cross-coupled with a second weak transistor. The integrated circuit may further include a first strong transistor in parallel with the first weak transistor and a second strong transistor in parallel with the second weak transistor. The integrated circuit may further include an inverter configured to toggle at least one of the first weak transistor and the second weak transistor.

公开(公告)号：US10333502B1

公开(公告)日：2019-06-25

申请号：US15936217

申请日：2018-03-26

Applicant: Cadence Design Systems, Inc.

Inventor： Abhinav Srivastava ,  Vinod Kumar

IPC: H03K3/00 ,  H03K3/356

Abstract: Various embodiments provide for a level shifter with sub-threshold voltage functionality, which permits the level shifter to operate even when a voltage supply to the level shifter falls below a normal operational voltage range of one or more devices (e.g., transistors) within the level shifter. A level shift of an embodiment may operate when a voltage supply falls below a normal operational range in order to save power, which can be useful with respect to battery-operated devices, such an Internet of Things (IoT) sensor.