公开(公告)号：US11323296B1

公开(公告)日：2022-05-03

申请号：US16943535

申请日：2020-07-30

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Sachin Ramesh Gugwad ,  Hari Anand Ravi ,  Thomas E Wilson ,  Vinod Kumar

IPC: H04L25/03 ,  H04L27/01

Abstract: The embodiments described herein provide for a method and system for training an optimal decision feedback equalization (DFE) coefficient for use in GDDR and DDR applications. The method includes determining a first expected bit pattern using a reference voltage. The method further includes determining a transition voltage value of the first expected bit pattern. The method further includes receiving a second expected bit pattern having a same first bit as the first expected bit pattern. The method further includes determining a transition voltage value of the second expected bit pattern using the reference voltage. The method further includes calculating an optimal reference voltage value by averaging the transition voltage values of the first expected bit pattern and the second-expected bit pattern and storing the optimal reference voltage value in a register corresponding to a logic value of the same first bit.

公开(公告)号：US10771108B1

公开(公告)日：2020-09-08

申请号：US16718004

申请日：2019-12-17

Applicant: Cadence Design Systems, Inc.

Inventor： H Md Shuaeb Fazeel ,  Sachin Ramesh Gugwad

IPC: H04B3/32 ,  H01L27/06 ,  H01R13/6464

Abstract: Embodiments relate to systems, methods, and computer-readable media to enable design and creation of crosstalk cancellation circuitry for a receiver (e.g. an AC coupled DDR5 receiver). One embodiment is a receiver apparatus with crosstalk victim and aggressors lines. The cancellation circuitry involves an amplifier and buffering circuitry to provide inductive and capacitive crosstalk cancellation voltages. Some embodiments can additionally involve circuitry for autozeroing modes for AC coupled receiver lines.

公开(公告)号：US11580048B1

公开(公告)日：2023-02-14

申请号：US16356939

申请日：2019-03-18

Applicant: Cadence Design Systems, Inc.

Inventor： Thomas E. Wilson ,  Scott Huss ,  Hari Anand Ravi ,  Sachin Ramesh Gugwad ,  Balbeer Singh Rathor

IPC: G06F9/30 ,  G06F13/42 ,  G06F1/12

Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for DDR reference voltage training. The method includes receiving a data stream, the data stream including pulses generated from a reference voltage in relation to a voltage input logic low and a voltage input logic high of an input stream. The method also includes receiving a clock signal, the clock signal including an in-phase signal and a quadrature-phase signal, the in-phase signal orthogonal to the quadrature-phase signal. The method also includes utilizing the in-phase signal and the quadrature-phase signal of the clock signal in relation to the data stream to obtain a stream of in-phase samples and a stream of quadrature-phase samples. The method also includes adjusting the reference voltage based on a relationship of the stream of in-phase samples to the stream of quadrature-phase samples.

公开(公告)号：US11483185B1

公开(公告)日：2022-10-25

申请号：US17246581

申请日：2021-04-30

Applicant: Cadence Design Systems, Inc.

Inventor： Sachin Ramesh Gugwad ,  Hari Anand Ravi ,  Aaron Willey ,  Thomas E. Wilson

IPC: H04L25/03

Abstract: Disclosed is an improved approach for a training approach to implement DFE for an electronic circuit. The inventive concept is particularity suitable to address, for example, circuits that implement high speed parallel data transmission protocols, such as GDDR6, that are used for graphics applications. The training scheme uses minimal hardware when compared to existing schemes by reusing calibration receiver in auto zeroing receiver as error receiver. Further it works for closed eyes by running the algorithm multiple times with gradual increase in complexity of training pattern, where DFE coefficients from previous iteration is used for the current iteration, thereby gradually opening the eye.

公开(公告)号：US12205673B1

公开(公告)日：2025-01-21

申请号：US17945902

申请日：2022-09-15

Applicant: Cadence Design Systems, Inc.

Inventor： Hari Anand Ravi ,  Sachin Ramesh Gugwad ,  Jitendra Kumar Yadav ,  Thomas Evan Wilson ,  Vinod Kumar

IPC: G11C8/18 ,  G06F1/12 ,  G06F13/20 ,  G11C7/22

Abstract: Various embodiments described herein provide for a read data strobe (RDQS) path having variation compensation (e.g., voltage and temperature compensation), delay lines, or both, where the RDQS path can be included by a physical (PHY) interface for a memory device, such as a Double Data Rate (DDR) Dynamic Random-Access Memory (DRAM) memory device.

公开(公告)号：US12183427B1

公开(公告)日：2024-12-31

申请号：US17967040

申请日：2022-10-17

Applicant: Cadence Design Systems, Inc.

Inventor： Sachin Ramesh Gugwad ,  Hari Anand Ravi

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/14 ,  G11C7/22

Abstract: The present disclosure relates to a system and method for duty cycle correction is provided. The method may include receiving a signal at a duty cycle adjuster and performing serializer clock duty cycle correction at the duty cycle adjuster. The method may further include performing true clock duty cycle correction at a transmitter duty cycle adjuster and performing complementary duty cycle distortion correction at the transmitter duty cycle adjuster.

公开(公告)号：US11979262B1

公开(公告)日：2024-05-07

申请号：US17569978

申请日：2022-01-06

Applicant: Cadence Design Systems, Inc.

Inventor： Hari Anand Ravi ,  Sachin Ramesh Gugwad

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03267

Abstract: Various embodiments provide for identifying and training a floating tap for decision feedback equalization. For some embodiments, the identification and training of the floating tap described herein can be part of a circuit for receiver block of a system, such as a memory system.

公开(公告)号：US09754646B1

公开(公告)日：2017-09-05

申请号：US15342974

申请日：2016-11-03

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar ,  Tara Vishin ,  Sachin Ramesh Gugwad ,  Thomas Evan Wilson

IPC: G11C7/12 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1012 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093

Abstract: Embodiments relate to circuits, electronic design automation (EDA) circuit layouts, systems, methods, and computer readable media to enable logic devices operating on a core supply voltage to drive memory devices operating on a different supply voltage using low power and high data rates while avoiding voltage over-stress of thin-oxide transistors. In an embodiment, channels of a thin-oxide PMOS transistor, a thick-oxide PMOS transistor, a thick-oxide NMOS transistor, and a thin-oxide NMOS transistor are coupled in order from a memory device voltage supply rail to a low voltage supply rail. Gates of the thin-oxide PMOS transistor and the thick-oxide NMOS transistor are coupled with an output of a flying capacitor circuit that level-shifts an input signal by a difference between the memory device supply and core supply voltages, while gates of the thick-oxide PMOS transistor and the thin-oxide NMOS transistor receive the input signal via a buffer.