公开(公告)号：US5599733A

公开(公告)日：1997-02-04

申请号：US342530

申请日：1994-11-21

Applicant: Chang-Feng Wan ,  John H. Tregilgas

Inventor： Chang-Feng Wan ,  John H. Tregilgas

IPC: H01L21/469 ,  H01L31/103 ,  H01L21/225

CPC classification number: H01L21/469 ,  H01L31/1032 ,  Y10S438/971

Abstract: A hybrid focal plane array has p-n junction photodiodes formed in a substrate (10) of HgCdTe which is passivated by a cap layer (12) of Cd-rich CdTe. The active surface of the HgCdTe substrate is passivated by annealing at a temperature sufficient to support interdiffusion between the Cd-rich CdTe capping layer (12) and the HgCdTe substrate (10). Use of the CdTe capping layer (12) with a slight excess Cd maintains the surface of the HgCdTe substrate (10) in a metal-rich phase condition.

Abstract translation: 混合焦平面阵列具有形成在HgCdTe的衬底（10）中的p-n结光电二极管，其被富含Cd的CdTe的覆盖层（12）钝化。 通过在足以支持富Cd的CdTe覆盖层（12）和HgCdTe衬底（10）之间的相互扩散的温度下退火来钝化HgCdTe衬底的活性表面。 使用具有轻微过量Cd的CdTe覆盖层（12）将HgCdTe衬底（10）的表面维持在富金相的状态。

公开(公告)号：US4968886A

公开(公告)日：1990-11-06

申请号：US400603

申请日：1989-08-30

Applicant: Chang-Feng Wan ,  Frank C. Sulzbach

Inventor： Chang-Feng Wan ,  Frank C. Sulzbach

IPC: H01L27/146 ,  H01L31/113

CPC classification number: H01L31/1133 ,  H01L27/14603 ,  H01L27/14649 ,  H01L27/14683

Abstract: Materials for infrared transparent, electrically conductive applications such as gate for infrared detectors made of titanium oxynitride (TiN.sub.x O.sub.y), bismuth, and antimony. Titanium oxynitride with resistivity of at least 0.001 .OMEGA.-cm provides sufficient transmittance for infrared detector gate application as illustrated in FIG. 4.

公开(公告)号：US07952189B2

公开(公告)日：2011-05-31

申请号：US11113545

申请日：2005-04-25

Applicant: Chang-Feng Wan

Inventor： Chang-Feng Wan

IPC: H01L23/12

CPC classification number: B81C1/00269 ,  H01L2924/16235 ,  Y10T156/1052

Abstract: An embodiment of the present invention provides a method of manufacturing hermetic packaging for devices on a substrate wafer, comprising forming a plurality of adhesive rings on a cap wafer or the substrate wafer, bonding the cap wafer to the substrate wafer with an adhesive layer, forming trenches in the cap wafer and the adhesive rings along outer rim of the adhesive rings, and covering sidewall of the trenches by at least one deposited film to provide a diffusion barrier to moisture or gas.

Abstract translation: 本发明的一个实施例提供了一种制造衬底晶片上器件的密封封装的方法，包括在盖晶片或衬底晶片上形成多个粘合环，将盖晶片与粘合剂层接合，形成 盖晶片中的沟槽和沿着粘合环的外边缘的粘合剂环，并且通过至少一个沉积膜覆盖沟槽的侧壁以提供对湿气或气体的扩散阻挡。

公开(公告)号：US07612340B2

公开(公告)日：2009-11-03

申请号：US11196100

申请日：2005-08-03

Applicant: Jeffrey Don Beck ,  Pradip Mitra ,  Chang-Feng Wan ,  Michael A. Kinch

Inventor： Jeffrey Don Beck ,  Pradip Mitra ,  Chang-Feng Wan ,  Michael A. Kinch

IPC: H01L31/107 ,  G01J5/20

CPC classification number: H01L31/02027 ,  H01L31/0296 ,  H01L31/02966 ,  H01L31/1032 ,  H01L31/105 ,  H01L31/107

Abstract: An avalanche photodiode is operated in avalanche mode at a selected reverse bias that achieves high gain and a reduced gain normalized dark current.

Abstract translation: 雪崩光电二极管以选择的反向偏置在雪崩模式下操作，其实现高增益和减小的标准化暗电流。

公开(公告)号：US20080308920A1

公开(公告)日：2008-12-18

申请号：US12028841

申请日：2008-02-11

Applicant: Chang-Feng Wan

Inventor： Chang-Feng Wan

IPC: H01L23/02

CPC classification number: G01L9/0042 ,  B81B2201/0264 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2203/0384 ,  B81B2207/07 ,  B81C1/00095 ,  B81C1/00285 ,  B81C1/00333 ,  B81C2201/019 ,  H01G5/16 ,  H01G5/40 ,  H01L29/82

Abstract: A system and method for manufacturing micro cavity packaging enclosure at the wafer level using MEMS (MicroElectroMechanical Systems) process, wherein micro cavities are formed from epoxy-bonded single-crystalline silicon wafer as its cap, epoxy and deposited metal or insulator as at least part of its sidewall, on substrate wafers.

Abstract translation: 一种用于使用MEMS（微电子机械系统）工艺在晶片级制造微腔封装外壳的系统和方法，其中微腔由环氧键合单晶硅晶片作为其盖，环氧树脂和沉积的金属或绝缘体形成为至少部分 的侧壁。

公开(公告)号：US07265477B2

公开(公告)日：2007-09-04

申请号：US11028409

申请日：2005-01-03

Applicant: Chang-Feng Wan

Inventor： Chang-Feng Wan

IPC: H02N1/00 ,  H01H59/00 ,  G02B26/00

CPC classification number: H02N1/006 ,  H01G5/16 ,  H01G5/38

Abstract: An embodiment of the present invention provides a stepping actuator, comprising a suspended membrane comprising a plurality of movable electrodes connected by plurality of spring hinges to a payload platform; and anchors connecting said membrane to a substrate, said substrate comprising a plurality of fixed electrodes; wherein said movable electrodes of said suspended membrane and said fixed electrodes from said substrate form parallel-plate electrostatic sub-actuators.

Abstract translation: 本发明的一个实施例提供了一种步进致动器，其包括悬挂膜，该悬浮膜包括由多个弹簧铰链连接到有效载荷平台的多个可移动电极; 以及将所述膜连接到基底上，所述基底包括多个固定电极; 其中所述悬浮膜的所述可移动电极和所述固定电极从所述衬底形成平行板静电副致动器。

公开(公告)号：US5959340A

公开(公告)日：1999-09-28

申请号：US707815

申请日：1996-08-30

Applicant: Chang-Feng Wan ,  Richard Scott List ,  Curtis Gene Garrett ,  Dwight U. Bartholomew

Inventor： Chang-Feng Wan ,  Richard Scott List ,  Curtis Gene Garrett ,  Dwight U. Bartholomew

IPC: H01L21/58 ,  H01L31/00

CPC classification number: H01L24/83 ,  H01L24/29 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/0132 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/351

Abstract: This invention relates to mounting integrated circuits (IC) to multi-chip modules (MCM) or substrates. More specifically, it provides a method of mounting a semiconductor die such as a thin slice of Mercury Cadmium Telluride (MCT) to a silicon semiconductor substrate, a read-out integrated circuit (ROIC), using a thermoplastic to reduce stress on the MCT caused by mismatched Coefficients of Thermal Expansion (CTE). This process provides for an array of infrared photodetectors on a material such as MCT to be mounted to a read-out integrated circuit (ROIC) using the Vertical Integrated Photodiode (VIP) approach to FPAs, while allowing double sided interdiffusion of CdTe for surface passivation to reduce dark currents and improve performance, without the problems associated with mismatched coefficients of thermal expansion during high temperature processes.

公开(公告)号：US5846850A

公开(公告)日：1998-12-08

申请号：US706583

申请日：1996-09-05

Applicant: Peter D. Dreiske ,  Chang-Feng Wan

Inventor： Peter D. Dreiske ,  Chang-Feng Wan

IPC: H01L27/146 ,  H01L31/18

CPC classification number: H01L27/1465

Abstract: This invention relates to a process and structure for performing a high temperature or other process on both sides of a thin slice of material or die prior to being placed onto a integrated circuit or multi-chip module. In a particular embodiment, a process and structure is given to provide for double sided interdiffusion for passivation of a Mercury Cadmium Telluride (MCT) film which is mounted to a read-out integrated circuit (ROIC) face side up in order to fabricate vertically integrated Focal Plane Arrays (FPAs) with reduced dark currents and improved performance. The process of the present invention also allows for the insertion of novel materials such as Double Layer Heterojunction (DLHJ), MBE, MOCVD, etc. in the vertical integrated approach to FPAs.

Abstract translation: 本发明涉及一种用于在被放置在集成电路或多芯片模块上之前在薄片材料或管芯的两侧执行高温或其它工艺的工艺和结构。 在特定实施例中，提供了一种工艺和结构来提供用于钝化碲化汞碲化镉（MCT）膜的双面相互扩散，其将面向一侧的面向上安装到读出集成电路（ROIC），以制造垂直集成 焦平面阵列（FPA）具有降低的暗电流和改进的性能。 本发明的方法还允许在垂直集成方法中插入诸如双层异质结（DLHJ），MBE，MOCVD等的新型材料。

公开(公告)号：US4474640A

公开(公告)日：1984-10-02

申请号：US326301

申请日：1981-12-01

Applicant: Chang-Feng Wan

Inventor： Chang-Feng Wan

IPC: C30B19/02 ,  C30B19/10

CPC classification number: C30B19/02 ,  C30B29/48

Abstract: For HgCdTe liquid phase epitaxy (LPE), in situ differential thermal analysis apparatus is used to precisely monitor the liquidus temperature of each HgCdTe melt. The neutral body, e.g. a slug of copper enclosed in a silica ampoule, is placed near the LPE reactor in a furnace. During heating or cooling, differential sensing of a pair of thermocouples (in the melt and in the neutral body) will show an accelerated change at transformation points, since at these points the temperature of the melt will be changed by the energy of the physical change, while that of the neutral body remains subject only to passive heat transfer. Thus, the actual liquidus temperature of each melt can be measured with extreme precision, and isothermal or programmed cooling methods of LPE can be precisely and reliably controlled under production conditions.

Abstract translation: 对于HgCdTe液相外延（LPE），使用原位差分热分析仪器精确监测每个HgCdTe熔体的液相线温度。 中性体，例如 将封闭在二氧化硅安瓿中的铜块放置在炉中的LPE反应器附近。 在加热或冷却过程中，一对热电偶（在熔体和中性体中）的差分感应将在相变点显示出加速的变化，因为在这些点上，熔体的温度将被物理变化的能量所改变 ，而中性身体的物体仍然只受到被动热传递。 因此，可以极精度地测量每个熔体的实际液相线温度，并且可以在生产条件下精确可靠地控制LPE的等温或程序冷却方法。

公开(公告)号：US20120264254A1

公开(公告)日：2012-10-18

申请号：US13421860

申请日：2012-03-16

Applicant: Chang-Feng Wan

Inventor： Chang-Feng Wan

IPC: H01L31/18

CPC classification number: H01L27/1443 ,  H01L31/02966 ,  H01L31/109 ,  H01L31/1832 ,  H01L31/1864 ,  Y02E10/50

Abstract: In the preferred embodiment of the present invention, narrow bandgap II-VI compound semiconductor HgxCd1-xTe (0.1≦x≦0.5) (HgCdTe) wafers are annealed under Cd supersaturated conditions by exposing the HgCdTe planar or mesa surfaces to a Cd molecular beam in a vacuum deposition system before, during, and/or after anneals performed during individual photodiode fabrication process steps or HgCdTe epitaxial growth steps for eliminating or neutralizing the bulk or interfacial defects.

Abstract translation: 在本发明的优选实施方案中，通过将HgCdTe平面或台面表面暴露于Cd分子束，在Cd过饱和条件下对窄带隙II-VI化合物半导体HgxCd1-xTe（0.1＆nlE; x＆nlE; 0.5）（HgCdTe） 在单个光电二极管制造工艺步骤中执行退火之前，期间和/或之后的真空沉积系统或用于消除或中和本体或界面缺陷的HgCdTe外延生长步骤。