公开(公告)号：US08541256B2

公开(公告)日：2013-09-24

申请号：US13421860

申请日：2012-03-16

Applicant: Chang-Feng Wan

Inventor： Chang-Feng Wan

IPC: H01L31/18

CPC classification number: H01L27/1443 ,  H01L31/02966 ,  H01L31/109 ,  H01L31/1832 ,  H01L31/1864 ,  Y02E10/50

Abstract: In the preferred embodiment of the present invention, narrow bandgap II-VI compound semiconductor HgxCd1-xTe (0.1≦x≦0.5) (HgCdTe) wafers are annealed under Cd supersaturated conditions by exposing the HgCdTe planar or mesa surfaces to a Cd molecular beam in a vacuum deposition system before, during, and/or after anneals performed during individual photodiode fabrication process steps or HgCdTe epitaxial growth steps for eliminating or neutralizing the bulk or interfacial defects.

Abstract translation: 在本发明的优选实施方案中，将窄带隙II-VI化合物半导体HgxCd1-xTe（0.1 @ x @ 0.5）（HgCdTe）晶片在Cd过饱和条件下退火，通过将HgCdTe平面或台面表面暴露于Cd分子束 在单个光电二极管制造工艺步骤中执行退火之前，期间和/或之后的真空沉积系统或用于消除或中和本体或界面缺陷的HgCdTe外延生长步骤。

公开(公告)号：US07579663B2

公开(公告)日：2009-08-25

申请号：US12028841

申请日：2008-02-11

Applicant: Chang-Feng Wan

Inventor： Chang-Feng Wan

IPC: H01L29/78

CPC classification number: G01L9/0042 ,  B81B2201/0264 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2203/0384 ,  B81B2207/07 ,  B81C1/00095 ,  B81C1/00285 ,  B81C1/00333 ,  B81C2201/019 ,  H01G5/16 ,  H01G5/40 ,  H01L29/82

Abstract: A system and method for manufacturing micro cavity packaging enclosure at the wafer level using MEMS (MicroElectroMechanical Systems) process, wherein micro cavities are formed from epoxy-bonded single-crystalline silicon wafer as its cap, epoxy and deposited metal or insulator as at least part of its sidewall, on substrate wafers.

Abstract translation: 一种用于使用MEMS（微电子机械系统）工艺在晶片级制造微腔封装外壳的系统和方法，其中微腔由环氧键合单晶硅晶片作为其盖，环氧树脂和沉积的金属或绝缘体形成为至少部分 的侧壁。

公开(公告)号：US5523241A

公开(公告)日：1996-06-04

申请号：US361902

申请日：1994-12-21

Applicant: Chang-Feng Wan ,  Joseph D. Luttmer ,  Julie S. England ,  David E. Fleming

Inventor： Chang-Feng Wan ,  Joseph D. Luttmer ,  Julie S. England ,  David E. Fleming

IPC: H01L27/146 ,  H01L21/8254

CPC classification number: H01L27/14649 ,  Y10S148/063

Abstract: Channel stops for MIS infrared photodetector devices in Hg.sub.1-x Cd.sub.x Te by lattice damage (454) between and automatically aligned to MIS gates (408). Also, field plates and guard rings are automatically aligned to MIS gates.

Abstract translation: 通过在Hg1-xCdxTe中的MIS红外光电检测器件的通道停止，通过晶格损伤（454）并自动对准MIS门（408）。 此外，现场板和保护环自动对准MIS门。

公开(公告)号：US20070222334A1

公开(公告)日：2007-09-27

申请号：US11277479

申请日：2006-03-24

Applicant: Chang-Feng Wan

Inventor： Chang-Feng Wan

IPC: H01G5/01 ,  G02B26/00 ,  H02N1/00

CPC classification number: G02B26/0841 ,  B81B3/0051 ,  B81B2201/038 ,  H01G5/18 ,  H01G5/38 ,  H02N1/006

Abstract: An embodiment of the present invention provides a step actuator, comprising a suspended membrane comprising a plurality of movable electrodes connected by plurality of spring hinges to a payload platform; and pillars connecting said membrane to a substrate, said substrate comprising a plurality of fixed electrodes; wherein said movable electrodes of said suspended membrane and said fixed electrodes from said substrate form parallel-plate electrostatic sub-actuators. Another embodiment of the present invention provides controlled operation of the step actuator over its entire range of motion, by avoiding its instability region and both digital and analog operations with enhanced stroke. It comprises a suspended membrane comprising a plurality of fixed electrodes, a plurality of movable electrodes connected by plurality of spring hinges to a medial payload platform. The fixed electrodes comprise insulator stops that keep the movable electrodes from entering the unstable region.

Abstract translation: 本发明的实施例提供了一种步进致动器，其包括悬浮膜，该悬浮膜包括通过多个弹簧铰链连接到有效载荷平台的多个可移动电极; 以及将所述膜连接到基底的柱，所述基底包括多个固定电极; 其中所述悬浮膜的所述可移动电极和所述固定电极从所述衬底形成平行板静电副致动器。 本发明的另一个实施例通过避免其不稳定区域以及具有增强的行程的数字和模拟操作来提供步进致动器在整个运动范围内的受控操作。 它包括悬浮膜，其包括多个固定电极，多个可动电极，通过多个弹簧铰链连接到内侧有效载荷平台。 固定电极包括使可动电极不进入不稳定区域的绝缘体止动件。

公开(公告)号：US20070029485A1

公开(公告)日：2007-02-08

申请号：US11196100

申请日：2005-08-03

Applicant: Jeffrey Beck ,  Pradip Mitra ,  Chang-Feng Wan ,  Michael Kinch

Inventor： Jeffrey Beck ,  Pradip Mitra ,  Chang-Feng Wan ,  Michael Kinch

IPC: H01L31/00 ,  H01L31/0296

CPC classification number: H01L31/02027 ,  H01L31/0296 ,  H01L31/02966 ,  H01L31/1032 ,  H01L31/105 ,  H01L31/107

Abstract: An avalanche photodiode is operated in avalanche mode at a selected reverse bias that achieves high gain and a reduced gain normalized dark current.

Abstract translation: 雪崩光电二极管以选择的反向偏置在雪崩模式下操作，其实现高增益和减小的标准化暗电流。

公开(公告)号：US6127203A

公开(公告)日：2000-10-03

申请号：US304953

申请日：1999-05-05

Applicant: Chang-Feng Wan ,  Richard Scott List ,  Curtis Gene Garrett ,  Dwight U. Bartholomew

Inventor： Chang-Feng Wan ,  Richard Scott List ,  Curtis Gene Garrett ,  Dwight U. Bartholomew

IPC: H01L21/58 ,  H01L21/324

CPC classification number: H01L24/83 ,  H01L24/29 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/0132 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/351

Abstract: This invention relates to mounting integrated circuits (IC) to multi-chip modules (MCM) or substrates. More specifically, it provides a method of mounting a semiconductor die such as a thin slice of Mercury Cadmium Telluride (MCT) to a silicon semiconductor substrate, a read-out integrated circuit (ROIC), using a thermoplastic to reduce stress on the MCT caused by mismatched Coefficients of Thermal Expansion (CTE). This process provides for an array of infrared photodetectors on a material such as MCT to be mounted to a read-out integrated circuit (ROIC) using the Vertical Integrated Photodiode (VIP) approach to FPAs, while allowing double sided interdiffusion of CdTe for surface passivation to reduce dark currents and improve performance, without the problems associated with mismatched coefficients of thermal expansion during high temperature processes.

Abstract translation: 本发明涉及将集成电路（IC）安装到多芯片模块（MCM）或基板上。 更具体地，它提供了一种将半导体管芯如汞碲化镉（MCT）的薄片安装到硅半导体衬底，读出集成电路（ROIC），使用热塑性材料以减少MCT上的应力的方法， 通过不匹配的热膨胀系数（CTE）。 该过程提供了在诸如MCT的材料上的红外光电检测器阵列，其将使用针对FPAs的垂直集成光电二极管（VIP）方法安装到读出集成电路（ROIC），同时允许CdTe用于表面钝化的双面相互扩散 以减少暗电流并提高性能，而没有与高温过程中热膨胀系数不匹配相关的问题。

公开(公告)号：US07541214B2

公开(公告)日：2009-06-02

申请号：US10213564

申请日：2002-08-07

Applicant: Chang-Feng Wan

Inventor： Chang-Feng Wan

IPC: H01L21/00

CPC classification number: B81C1/00095 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2207/07 ,  B81C2201/019

Abstract: The present invention is related to a method for manufacturing micro-electro-mechanical systems (MEMS) having movable and stationary suspended structures formed from mono-crystalline silicon wafer or chip, bonded to a substrate wafer with an polymer adhesive layer that serves as spacer and as a sacrificial layer which is undercut by dry etch means. The substrate wafer contains electronic circuits for sensing and actuating the suspended structure by electrical means. Electrical interconnections between the suspended structures and the substrate can be made by etching through via holes in the suspended structure and the adhesive, depositing metal layers in the via holes, and removing the metal layers from outside the via holes. The metal layers in the via holes can also be used as pillars for supporting the suspended structures. This method can be used to manufacture inertial sensors.

Abstract translation: 本发明涉及一种用于制造微机电系统（MEMS）的方法，所述微机电系统（MEMS）具有由单晶硅晶片或芯片形成的可移动和固定的悬挂结构，其结合到具有用作间隔物的聚合物粘合剂层的衬底晶片， 作为通过干式蚀刻手段进行底切的牺牲层。 基板晶片包含电子电路，用于通过电气装置检测和致动悬挂结构。 悬浮结构和基板之间的电互连可以通过蚀刻通过悬浮结构中的通孔和粘合剂，在通孔中沉积金属层，以及从通孔外部去除金属层来制成。 通孔中的金属层也可以用作用于支撑悬挂结构的支柱。 该方法可用于制造惯性传感器。

公开(公告)号：US07429495B2

公开(公告)日：2008-09-30

申请号：US10712196

申请日：2003-11-13

Applicant: Chang-Feng Wan

Inventor： Chang-Feng Wan

IPC: H01L21/00

CPC classification number: G01L9/0042 ,  B81B2201/0264 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2203/0384 ,  B81B2207/07 ,  B81C1/00095 ,  B81C1/00285 ,  B81C1/00333 ,  B81C2201/019 ,  H01G5/16 ,  H01G5/40 ,  H01L29/82

Abstract: A system and method for manufacturing micro cavities at the wafer level using a unique, innovative MEMS (MicroElectroMechanical Systems) process, wherein micro cavities are formed, with epoxy bonded single-crystalline silicon membrane as cap and deposited and/or electroplated metal as sidewall, on substrate wafers. The epoxy is also the sacrificial layer. It is removed from within the cavity through small etch access holes etched in the silicon cap before the etch access holes are sealed under vacuum. The micro cavities manufactured therein can be used as pressure sensors or for packaging MEMS devices under vacuum or inert environment. In addition, the silicon membrane manufactured therein can be used to manufacture RF switches.

Abstract translation: 一种使用独特的创新MEMS（微电子机械系统）工艺在晶片级制造微腔的系统和方法，其中形成微腔，其中环氧键合单晶硅膜作为盖并且沉积和/或电镀金属作为侧壁， 在衬底晶圆上。 环氧树脂也是牺牲层。 在蚀刻访问孔在真空下密封之前，通过蚀刻在硅帽中的小蚀刻访问孔从腔体内移除。 其中制造的微孔可用作压力传感器或用于在真空或惰性环境下包装MEMS器件。 此外，其中制造的硅膜可以用于制造RF开关。

公开(公告)号：US20080138922A1

公开(公告)日：2008-06-12

申请号：US10213564

申请日：2002-08-07

Applicant: Chang-Feng Wan

Inventor： Chang-Feng Wan

IPC: H01L21/30

CPC classification number: B81C1/00095 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2207/07 ,  B81C2201/019

Abstract: The present invention is related to a method for manufacturing micro-electro-mechanical systems (MEMS) having movable and stationary suspended structures formed from mono-crystalline silicon wafer or chip, bonded to a substrate wafer with an polymer adhesive layer that serves as spacer and as a sacrificial layer which is undercut by dry etch means. The substrate wafer contains electronic circuits for sensing and actuating the suspended structure by electrical means. Electrical interconnections between the suspended structures and the substrate can be made by etching through via holes in the suspended structure and the adhesive, depositing metal layers in the via holes, and removing the metal layers from outside the via holes. The metal layers in the via holes can also be used as pillars for supporting the suspended structures. This method can be used to manufacture inertial sensors.

Abstract translation: 本发明涉及一种用于制造微机电系统（MEMS）的方法，所述微机电系统（MEMS）具有由单晶硅晶片或芯片形成的可移动和固定的悬挂结构，其结合到具有用作间隔物的聚合物粘合剂层的衬底晶片， 作为通过干式蚀刻手段进行底切的牺牲层。 基板晶片包含电子电路，用于通过电气装置检测和致动悬挂结构。 悬浮结构和基板之间的电互连可以通过蚀刻通过悬浮结构中的通孔和粘合剂，在通孔中沉积金属层，以及从通孔外部去除金属层来制成。 通孔中的金属层也可以用作用于支撑悬挂结构的支柱。 该方法可用于制造惯性传感器。

公开(公告)号：US07265429B2

公开(公告)日：2007-09-04

申请号：US10858017

申请日：2004-06-01

Applicant: Chang-Feng Wan

Inventor： Chang-Feng Wan

IPC: H01L29/84

CPC classification number: G01L9/0042 ,  B81B2201/0264 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2203/0384 ,  B81B2207/07 ,  B81C1/00095 ,  B81C1/00285 ,  B81C1/00333 ,  B81C2201/019 ,  G01J3/26 ,  H01L29/82

Abstract: A system and method for manufacturing micro cavities at the wafer level using a unique, innovative MEMS (MicroElectroMechanical Systems) process, wherein micro cavities are formed, with epoxy bonded single-crystalline silicon membrane as cap and deposited and/or electroplated metal as sidewall, on substrate wafers. The epoxy is also the sacrificial layer. It is totally removed from within the cavity through small etch access holes etched in the silicon cap before the etch access holes are sealed under vacuum. The micro cavities manufactured therein can be used as pressure sensors or for packaging MEMS devices under vacuum or inert environment. In addition, the silicon membrane manufactured therein can be used to manufacture RF switches.

Abstract translation: 一种使用独特的创新MEMS（微电子机械系统）工艺在晶片级制造微腔的系统和方法，其中形成微腔，其中环氧键合单晶硅膜作为盖并且沉积和/或电镀金属作为侧壁， 在衬底晶圆上。 环氧树脂也是牺牲层。 在蚀刻访问孔在真空下密封之前，通过蚀刻在硅帽中的小蚀刻访问孔，完全从腔内移除。 其中制造的微孔可用作压力传感器或用于在真空或惰性环境下包装MEMS器件。 此外，其中制造的硅膜可以用于制造RF开关。