公开(公告)号：US5317192A

公开(公告)日：1994-05-31

申请号：US879190

申请日：1992-05-06

申请人： Fusen E. Chen ,  Girish A. Dixit ,  Che-Chia Wei

发明人： Fusen E. Chen ,  Girish A. Dixit ,  Che-Chia Wei

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/400

CPC分类号： H01L23/5226 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002

摘要： A method is provided for forming an integrated circuit contact structure. A conductive region is formed on a semiconductor device. Thereafter an insulating layer is formed over the conductive region. An opening is then formed through the insulating region to the conductive region. A thin barrier layer is deposited over the integrated circuit contact structure. A portion of the thin barrier layer is removed by backsputtering the integrated circuit contact structure so that only a thin barrier sidewall remains. Finally, a conductive metal layer is deposited over the integrated circuit contact structure. In one embodiment, the integrated circuit contact structure is baked before the conductive metal layer is deposited.

摘要翻译： 提供了一种用于形成集成电路接触结构的方法。 在半导体器件上形成导电区域。 此后，在导电区域上形成绝缘层。 然后通过绝缘区域形成到导电区域的开口。 薄的势垒层沉积在集成电路接触结构上。 通过反向溅射集成电路接触结构来去除薄势垒层的一部分，使得只有薄的阻挡侧壁保留。 最后，在集成电路接触结构上沉积导电金属层。 在一个实施例中，在沉积导电金属层之前烘烤集成电路接触结构。

公开(公告)号：US5246883A

公开(公告)日：1993-09-21

申请号：US832088

申请日：1992-02-06

申请人： Yih-Shung Lin ,  Lun-Tseng Lu ,  Fu-Tai Liou ,  Che-Chia Wei ,  John L. Walters

发明人： Yih-Shung Lin ,  Lun-Tseng Lu ,  Fu-Tai Liou ,  Che-Chia Wei ,  John L. Walters

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522

CPC分类号： H01L23/485 ,  H01L21/76804 ,  H01L2924/0002

摘要： A method is provided for forming contact vias in an integrated circuit. Initially, a first buffer layer is formed over an insulating layer in an integrated circuit. The first buffer layer has a different etch rate from the insulating layer. A second buffer layer is then formed over the first buffer layer, with the second buffer layer having an etch rate which is faster than the first buffer layer. An isotropic etch is performed to create an opening through the second buffer layer and a portion of the first buffer layer. Because the second buffer layer etches faster than the first buffer layer, the slant of the sideswalls of the opening can be controlled. An anisotropic etch is then performed to complete formation of the contact via.

公开(公告)号：US4788160A

公开(公告)日：1988-11-29

申请号：US32836

申请日：1987-03-31

申请人： Robert H. Havemann ,  Roger A. Haken ,  Thomas E. Tang ,  Che-Chia Wei

发明人： Robert H. Havemann ,  Roger A. Haken ,  Thomas E. Tang ,  Che-Chia Wei

IPC分类号： H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L29/45 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L29/456 ,  Y10S148/105 ,  Y10S148/147 ,  Y10S438/923

摘要： A process for forming shallow silicided junctions includes the step of sputtering a layer of titanium (28) over a moat region to cover a gate electrode (18) and a sidewall oxide (22) formed on the sidewalls of the gate electrode (18). The titanium is reacted with exposed silicon regions (24) and (26) to form silicide layers (30) and (32) and then dopant impurities are implanted into the substrate (10) prior to stripping the unreacted titanium. The unreacted titanium (36), (38), or (40) functions as a mask to both offset the implanted regions from the channel region (20) under the gate electrode (18) and also to prevent impurities from entering the substrate at regions outside the defined moat region.

摘要翻译： 形成浅硅化物结的方法包括在护城河区域上溅射钛（28）层以覆盖形成在栅电极（18）的侧壁上的栅电极（18）和侧壁氧化物（22）的步骤。 钛与暴露的硅区（24）和（26）反应以形成硅化物层（30）和（32），然后在汽提未反应的钛之前将掺杂剂杂质注入到衬底（10）中。 未反应的钛（36），（38）或（40）起到掩模的作用，以将注入区域从栅电极（18）下方的沟道区域（20）偏移，并且还防止杂质在区域 在定义的护城河地区之外。

公开(公告)号：US06313034B1

公开(公告)日：2001-11-06

申请号：US08510765

申请日：1995-08-03

申请人： Yang Pan ,  Che-Chia Wei

发明人： Yang Pan ,  Che-Chia Wei

IPC分类号： H01L2128

CPC分类号： H01L21/823418 ,  H01L21/76202 ,  H01L21/823468 ,  H01L21/823481

摘要： A method for forming integrated circuit device structures upon active semiconductor regions of a semiconductor substrate. The active semiconductor regions are defined by Field OXide (FOX) isolation regions which are formed through a Polysilicon Buffered LOCal Oxidation of Silicon (PBLOCOS) oxidation mask structure. The PBLOCOS oxidation mask structure includes a blanket pad oxide layer which resides upon the semiconductor substrate, a blanket polysilicon buffer layer which resides upon the blanket pad oxide layer and a patterned silicon nitride layer which resides upon the blanket polysilicon buffer layer. Portions of the blanket polysilicon buffer layer and the blanket pad oxide layer exposed through the patterned silicon nitride layer are completely consumed to leave remaining the patterned silicon nitride layer, a patterned polysilicon buffer layer and a patterned pad oxide layer upon the active regions of the semiconductor substrate which are separated by the FOX isolation regions. The portions of the patterned silicon nitride layer, the patterned polysilicon buffer layer and the patterned pad oxide layer are employed in forming integrated circuit device structures upon the active semiconductor region of the semiconductor substrate.

摘要翻译： 一种用于在半导体衬底的有源半导体区域上形成集成电路器件结构的方法。 活性半导体区域由通过硅（PBLOCOS）氧化掩模结构的多晶硅缓冲局部氧化形成的场OXide（FOX）隔离区限定。 PBLOCOS氧化掩模结构包括位于半导体衬底上的覆盖层氧化物层，驻留在覆盖层氧化物层上的覆盖多晶硅缓冲层和驻留在覆盖多晶硅缓冲层上的图案化氮化硅层。 通过图案化氮化硅层暴露的覆盖多晶硅缓冲层和覆盖层氧化物层的部分被完全消耗以留下图案化的氮化硅层，在半导体的有源区上留下图案化的多晶硅缓冲层和图案化的衬垫氧化物层 由FOX隔离区隔开的衬底。 图案化氮化硅层，图案化多晶硅缓冲层和图案化衬垫氧化物层的部分用于在半导体衬底的有源半导体区域上形成集成电路器件结构。

公开(公告)号：US5977607A

公开(公告)日：1999-11-02

申请号：US447362

申请日：1995-05-23

申请人： Robert Louis Hodges ,  Frank Randolph Bryant ,  Fusen E. Chen ,  Che-Chia Wei

发明人： Robert Louis Hodges ,  Frank Randolph Bryant ,  Fusen E. Chen ,  Che-Chia Wei

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L29/00

CPC分类号： H01L21/32 ,  H01L21/76202

摘要： A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over a portion of a substrate. A first silicon nitride layer is formed over the pad oxide layer. A polysilicon buffer layer is then formed over the first silicon nitride layer. A second silicon nitride layer is formed over the polysilicon layer. A photoresist layer is formed and patterned over the second silicon nitride layer. An opening is etched through the second silicon nitride layer and the polysilicon buffer layer to expose a portion of the first silicon nitride layer. A third silicon nitride region is then formed on at least the polysilicon buffer layer exposed in the opening. The first silicon nitride layer is etched in the opening. A field oxide region is then formed in the opening.

摘要翻译： 提供一种用于形成集成电路的隔离氧化物区域的方法和根据该集成电路形成的集成电路。 在衬底的一部分上形成衬垫氧化物层。 在衬垫氧化物层上形成第一氮化硅层。 然后在第一氮化硅层上形成多晶硅缓冲层。 在多晶硅层上形成第二氮化硅层。 在第二氮化硅层上形成并图案化光致抗蚀剂层。 通过第二氮化硅层和多晶硅缓冲层蚀刻开口以暴露第一氮化硅层的一部分。 至少在开口中暴露的多晶硅缓冲层上形成第三氮化硅区域。 在开口中蚀刻第一氮化硅层。 然后在开口中形成场氧化物区域。

公开(公告)号：US5894158A

公开(公告)日：1999-04-13

申请号：US769185

申请日：1991-09-30

申请人： Che-Chia Wei

发明人： Che-Chia Wei

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/76 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/66492 ,  H01L21/823814 ,  H01L29/6659

摘要： A mask is used for lightly doped drain and halo implants in an integrated circuit device. The mask exposes only portions of the substrate adjacent to field effect transistor gate electrodes. Since the halo implant is made only near the transistor channels, where it performs a useful function, adequate device reliability and performance is obtained. Since the halo implant is masked from those portions of the active regions for which it is not necessary, active region junction capacitances are lowered. Such lowered capacitances result in an improved transistor switching speed. The mask used to define the lightly doped drain and halo implant region can be easily formed from a straight forward combination of already existing gate and active area geometries.

摘要翻译： 掩模用于集成电路器件中的轻掺杂漏极和光晕注入。 掩模只露出与场效应晶体管栅电极相邻的衬底的部分。 由于光晕植入仅在晶体管通道附近进行，在其中它执行有用的功能，因此获得了足够的器件可靠性和性能。 由于从不需要的有源区的那些部分掩盖光晕注入，所以有源区域结电容降低。 这种降低的电容导致提高的晶体管切换速度。 用于限定轻掺杂的漏极和晕圈注入区域的掩模可以容易地由已经存在的栅极和有源区域几何形状的直接组合形成。

公开(公告)号：US5595935A

公开(公告)日：1997-01-21

申请号：US418191

申请日：1995-04-07

申请人： Tsiu C. Chan ,  Frank R. Bryant ,  Lun-Tseng Lu ,  Che-Chia Wei

发明人： Tsiu C. Chan ,  Frank R. Bryant ,  Lun-Tseng Lu ,  Che-Chia Wei

IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L21/28

CPC分类号： H01L23/5283 ,  H01L23/53271 ,  H01L2924/0002

摘要： A structure and method for fabricating intergrated circuit which provides for the detection of residual conductive material. A first conductive layer is deposited over the intergrated circuit and patterned to define a first interconnect layer. An insulating layer in then formed over the integrated circuit. A second conductive layer is then deposited and patterned to define a second interconnect layer. Residual conductive material can be formed during pattering of the second interconnect layer when portions of the second conductive layer remain adjacent to the vertical sidewalls of the first interconnect layer. To make the residual conductive material easier to detect, the conductivity of the residual conductive material is increased by either implanting impurities into the integrated circuit or siliciding the residual conductive material with a refractory metal.

摘要翻译： 用于制造集成电路的结构和方法，其提供残留导电材料的检测。 第一导电层沉积在集成电路上并被图案化以限定第一互连层。 然后形成在集成电路上的绝缘层。 然后沉积和图案化第二导电层以限定第二互连层。 当第二导电层的部分保持与第一互连层的垂直侧壁相邻时，可以在第二互连层的图形期间形成剩余的导电材料。 为了使残留的导电材料更易于检测，通过将杂质注入集成电路或用难熔金属硅化残留的导电材料来增加剩余导电材料的导电性。

公开(公告)号：US5346860A

公开(公告)日：1994-09-13

申请号：US088197

申请日：1993-07-06

申请人： Che-Chia Wei

发明人： Che-Chia Wei

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L21/283

CPC分类号： H01L21/76889 ,  H01L21/76895

摘要： A method for fabricating an interconnect structure in an integrated circuit. A first conductive layer is formed over an underlying region in the integrated circuit. The underlying region may be, for example, a semiconductor substrate or a gate electrode. A buffer layer is then formed over the first conductive layer, followed by the formation of an insulating layer over the buffer layer. The insulating layer and the buffer layer are patterned to define a form for the interconnect structure. A second conductive layer is then formed over the integrated circuit, and portions of the first conductive layer, the second conductive layer, and the buffer layer are silicided to form the interconnect structure.

摘要翻译： 一种用于在集成电路中制造互连结构的方法。 在集成电路中的下部区域上形成第一导电层。 下面的区域可以是例如半导体衬底或栅电极。 然后在第一导电层上形成缓冲层，随后在缓冲层上形成绝缘层。 将绝缘层和缓冲层图案化以限定互连结构的形式。 然后在集成电路上形成第二导电层，并且将第一导电层，第二导电层和缓冲层的部分硅化以形成互连结构。

公开(公告)号：US5043778A

公开(公告)日：1991-08-27

申请号：US238978

申请日：1988-08-25

申请人： Clarence W. Teng ,  Thomas E. Tang ,  Che-Chia Wei

发明人： Clarence W. Teng ,  Thomas E. Tang ,  Che-Chia Wei

IPC分类号： H01L21/285 ,  H01L21/308 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/66636 ,  H01L21/28525 ,  H01L21/3086 ,  H01L21/76218 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0847 ,  H01L27/0921 ,  H01L27/0928 ,  Y10S257/90

摘要： A MOS bulk device having source/drain-contact regions 36 which are almost completely isolated by a dielectric 35. These "source/drain" regions 36 formed by using a silicon etch to form a recess, limiting the etched recess with oxide, and backfilling with polysilicon. A short isotropic oxide etch, followed by a polysilicon filament deposition, then makes contact between the oxide-isolated source/drain-contact regions 36 and the channel region 33 of the active device. Outdiffusion through the small area of this contact will form small diffusioins 44 in silicon, which act as the electrically effective source/drain regions. Use of sidewall nitride filaments 30 on the gate permits the silicon etch step to be self-aligned.

摘要翻译： 具有源极/漏极 - 接触区域36的MOS体器件，其几乎完全由电介质35隔离。这些通过使用硅蚀刻形成凹槽形成的“源极/漏极”区域36，用氧化物限制蚀刻的凹槽，并且填充 与多晶硅。 短的各向同性氧化物蚀刻，随后是多晶硅长丝沉积，然后在氧化物隔离的源极/漏极 - 接触区域36和有源器件的沟道区域33之间接触。 通过该接触的小面积的扩散将在硅中形成小的漫射体44，其作为电学有效的源极/漏极区域。 在栅极上使用侧壁氮化物细丝30允许硅蚀刻步骤自对准。

公开(公告)号：US4920073A

公开(公告)日：1990-04-24

申请号：US350429

申请日：1989-05-11

申请人： Che-Chia Wei ,  Thomas E. Tang ,  James G. Bohlman ,  Monte A. Douglas

发明人： Che-Chia Wei ,  Thomas E. Tang ,  James G. Bohlman ,  Monte A. Douglas

IPC分类号： H01L21/3205 ,  H01L21/28 ,  H01L21/321 ,  H01L21/336 ,  H01L23/52

CPC分类号： H01L29/665 ,  H01L21/3211 ,  Y10S148/113 ,  Y10S148/147

摘要： The present invention provides a method for inhibiting the oxidation of a titanium layer during the direct reaction of the titanium with exposed silicon areas of an integrated circuit. In one embodiment of the present invention, a titanium nitride layer is formed on the surface of the titanium layer in the reactor where the titanium layer is deposited. The titanium nitride layer provides an effective barrier against oxidation. Thus, the formation of titanium dioxide is inhibited. In addition, in those areas where titanium nitride local interconnect is to be formed between diffused areas, the extra thickness provided by the top titanium nitride layer adds in the integrity of the conductive layers. By conducting the silicidation in a nitride atmosphere, diffusion of the nitride from the titanium nitride layer into the titanium layer and substitution of those lost nitrogen atoms by the atmosphere occurs thus providing a blocking layer for the formation of titanium silicide shorts.

摘要翻译： 本发明提供了在钛与集成电路的暴露的硅区域的直接反应期间抑制钛层的氧化的方法。 在本发明的一个实施例中，在沉积钛层的反应器中的钛层的表面上形成氮化钛层。 氮化钛层提供了抗氧化的有效屏障。 因此，二氧化钛的形成被抑制。 此外，在要在扩散区域之间形成氮化钛局部互连的区域中，由顶部氮化钛层提供的额外的厚度增加了导电层的完整性。 通过在氮化物气氛中进行硅化，氮化物从钛氮化物层扩散到钛层中，并且由于大气中的那些失去的氮原子而被发生，从而提供用于形成硅化钛短路的阻挡层。