公开(公告)号：US08441097B2

公开(公告)日：2013-05-14

申请号：US12646957

申请日：2009-12-23

申请人： Joseph M. Steigerwald ,  Nick Lindert ,  Steven J. Keating ,  Christopher J. Jezewski ,  Timothy E. Glassman

发明人： Joseph M. Steigerwald ,  Nick Lindert ,  Steven J. Keating ,  Christopher J. Jezewski ,  Timothy E. Glassman

IPC分类号： H01L21/02

CPC分类号： H01L28/90 ,  H01L27/0733

摘要： Methods to form memory devices having a MIM capacitor with a recessed electrode are described. In one embodiment, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes.

摘要翻译： 描述形成具有凹陷电极的MIM电容器的存储器件的方法。 在一个实施例中，形成具有凹陷电极的MIM电容器的方法包括形成由形成底部的下部和形成挖掘特征的侧壁的上部限定的挖掘特征。 该方法包括在特征中沉积下电极层，在下电极层上沉积电绝缘层，以及在电绝缘层上沉积上电极层以形成MIM电容器。 该方法包括去除MIM电容器的上部以暴露电极层的上表面，然后选择性地蚀刻电极层之一以使一个电极层凹陷。 该凹槽将电极彼此隔离并且减小了电极之间的电流泄漏路径的可能性。

公开(公告)号：US20110147888A1

公开(公告)日：2011-06-23

申请号：US12646957

申请日：2009-12-23

申请人： Joseph M. Steigerwald ,  Nick Lindert ,  Steven J. Keating ,  Christopher J. Jezewski ,  Timothy E. Glassman

发明人： Joseph M. Steigerwald ,  Nick Lindert ,  Steven J. Keating ,  Christopher J. Jezewski ,  Timothy E. Glassman

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/90 ,  H01L27/0733

摘要： Methods to form memory devices having a MIM capacitor with a recessed electrode are described. In one embodiment, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes.

摘要翻译： 描述形成具有凹陷电极的MIM电容器的存储器件的方法。 在一个实施例中，形成具有凹陷电极的MIM电容器的方法包括形成由形成底部的下部和形成挖掘特征的侧壁的上部限定的挖掘特征。 该方法包括在特征中沉积下电极层，在下电极层上沉积电绝缘层，以及在电绝缘层上沉积上电极层以形成MIM电容器。 该方法包括去除MIM电容器的上部以暴露电极层的上表面，然后选择性地蚀刻电极层之一以使一个电极层凹陷。 该凹槽将电极彼此隔离并且减小了电极之间的电流泄漏路径的可能性。

公开(公告)号：US07927959B2

公开(公告)日：2011-04-19

申请号：US12286338

申请日：2008-09-30

申请人： Steven J. Keating ,  Nick Lindert ,  Nadia Rahhal-Orabi ,  Brian Doyle ,  Satyarth Suri ,  Swaminathan Sivakumar ,  Lana Jong ,  Lin Sha

发明人： Steven J. Keating ,  Nick Lindert ,  Nadia Rahhal-Orabi ,  Brian Doyle ,  Satyarth Suri ,  Swaminathan Sivakumar ,  Lana Jong ,  Lin Sha

IPC分类号： H01L21/467

CPC分类号： H01L28/40 ,  H01G4/012 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/90 ,  H01L28/91 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.

摘要翻译： 在挖掘特征（130,330,830）的垂直侧壁（132,332,832）上图案化金属（141,341,841）的方法包括将材料（350）放置在挖掘的特征中，使得部分 （435）暴露在材料上方的挖掘特征中，使用第一湿蚀刻化学法将金属的暴露部分从垂直侧壁上蚀刻出来，并且通过使用第二湿蚀刻化学法将其去除，从挖掘的特征中去除材料 湿蚀刻化学。 所描述的方法可以用于产生适合于eDRAM器件的MIM电容器（800）。

公开(公告)号：US06667232B2

公开(公告)日：2003-12-23

申请号：US09208268

申请日：1998-12-08

申请人： Steven J. Keating ,  Robert S. Chau ,  Reza Arghavani ,  Jack T. Kavalieros ,  Douglas W. Barlage

发明人： Steven J. Keating ,  Robert S. Chau ,  Reza Arghavani ,  Jack T. Kavalieros ,  Douglas W. Barlage

IPC分类号： H01L214763

CPC分类号： H01L21/0214 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3143 ,  H01L29/51 ,  H01L29/518 ,  H01L2924/0002 ,  Y10S438/954 ,  H01L2924/00

摘要： A method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET includes passivating the surface of a semiconductor substrate at a temperature less than approximately 80° C. and nitridizing the passivation layer. In particular embodiments, passivating a silicon wafer includes forming a hydroxy-silicate layer at approximately 24° C. In a further aspect of the present invention, an integrated circuit includes a plurality of insulated gate field effect transistors, wherein various ones of the plurality of transistors have gate dielectric layers of the nitridized passivation layer.

摘要翻译： 形成适合用作MOSFET中的栅介质层的电介质层的方法包括在低于大约80℃的温度下钝化半导体衬底的表面并使钝化层氮化。 在特定实施例中，钝化硅晶片包括在约24℃下形成羟基硅酸盐层。在本发明的另一方面，集成电路包括多个绝缘栅场效应晶体管，其中多个 晶体管具有氮化钝化层的栅介质层。

公开(公告)号：US07494858B2

公开(公告)日：2009-02-24

申请号：US11173660

申请日：2005-06-30

申请人： Mark T. Bohr ,  Steven J. Keating ,  Thomas A. Letson ,  Anand S. Murthy ,  Donald W. O'Neill ,  Willy Rachmady

发明人： Mark T. Bohr ,  Steven J. Keating ,  Thomas A. Letson ,  Anand S. Murthy ,  Donald W. O'Neill ,  Willy Rachmady

IPC分类号： H01L21/336

CPC分类号： H01L29/045 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.

摘要翻译： 实施例是改进的晶体管结构和制造该结构的方法。 特别地，实施例的湿蚀刻形成具有改进的尖端形状的源极和漏极区域，以通过改善短沟道效应的控制，增加饱和电流，改善冶金栅极长度的控制，增加载流子迁移率来提高晶体管的性能 并且在源极和漏极与硅化物之间的界面处降低接触电阻。

公开(公告)号：US06953719B2

公开(公告)日：2005-10-11

申请号：US10851360

申请日：2004-05-20

申请人： Mark Doczy ,  Justin K. Brask ,  Steven J. Keating ,  Chris E. Barns ,  Brian S. Doyle ,  Michael L. McSwiney ,  Jack T. Kavalieros ,  John P. Barnak

发明人： Mark Doczy ,  Justin K. Brask ,  Steven J. Keating ,  Chris E. Barns ,  Brian S. Doyle ,  Michael L. McSwiney ,  Jack T. Kavalieros ,  John P. Barnak

IPC分类号： H01L21/3213 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/66545 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7833 ,  Y10S438/926

摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

公开(公告)号：US20080135894A1

公开(公告)日：2008-06-12

申请号：US12009122

申请日：2008-01-15

申请人： Mark T. Bohr ,  Steven J. Keating ,  Thomas A. Letson ,  Anand S. Murthy ,  Donald W. O'Neill ,  Willy Rachmady

发明人： Mark T. Bohr ,  Steven J. Keating ,  Thomas A. Letson ,  Anand S. Murthy ,  Donald W. O'Neill ,  Willy Rachmady

IPC分类号： H01L29/94

CPC分类号： H01L29/045 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.

摘要翻译： 实施例是改进的晶体管结构和制造该结构的方法。 特别地，实施例的湿蚀刻形成具有改进的尖端形状的源极和漏极区域，以通过改善短沟道效应的控制，增加饱和电流，改善冶金栅极长度的控制，增加载流子迁移率来提高晶体管的性能 并且在源极和漏极与硅化物之间的界面处降低接触电阻。

公开(公告)号：US06972225B2

公开(公告)日：2005-12-06

申请号：US10946502

申请日：2004-09-20

申请人： Mark Doczy ,  Justin K. Brask ,  Steven J. Keating ,  Chris E. Barns ,  Brian S. Doyle ,  Michael L. McSwiney ,  Jack T. Kavalieros ,  John P. Barnak

发明人： Mark Doczy ,  Justin K. Brask ,  Steven J. Keating ,  Chris E. Barns ,  Brian S. Doyle ,  Michael L. McSwiney ,  Jack T. Kavalieros ,  John P. Barnak

IPC分类号： H01L21/3213 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/66545 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7833 ,  Y10S438/926

摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

摘要翻译： 至少p型和n型半导体器件沉积在包含金属或金属合金栅极的半导体晶片上。 更具体地，在具有n型和p型金属栅极的半导体晶片上形成互补金属氧化物半导体（CMOS）器件。

公开(公告)号：US06858483B2

公开(公告)日：2005-02-22

申请号：US10327293

申请日：2002-12-20

申请人： Mark Doczy ,  Justin K. Brask ,  Steven J. Keating ,  Chris E. Barns ,  Brian S. Doyle ,  Michael L. McSwiney ,  Jack T. Kavalieros ,  John P. Barnak

发明人： Mark Doczy ,  Justin K. Brask ,  Steven J. Keating ,  Chris E. Barns ,  Brian S. Doyle ,  Michael L. McSwiney ,  Jack T. Kavalieros ,  John P. Barnak

IPC分类号： H01L21/3213 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/66545 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7833 ,  Y10S438/926

摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

摘要翻译： 至少p型和n型半导体器件沉积在包含金属或金属合金栅极的半导体晶片上。 更具体地，在具有n型和p型金属栅极的半导体晶片上形成互补金属氧化物半导体（CMOS）器件。

公开(公告)号：US07316949B2

公开(公告)日：2008-01-08

申请号：US11248737

申请日：2005-10-11

申请人： Mark Doczy ,  Justin K. Brask ,  Steven J. Keating ,  Chris E. Barns ,  Brian S. Doyle ,  Michael L. McSwiney ,  Jack T. Kavalieros ,  John P. Barnak

发明人： Mark Doczy ,  Justin K. Brask ,  Steven J. Keating ,  Chris E. Barns ,  Brian S. Doyle ,  Michael L. McSwiney ,  Jack T. Kavalieros ,  John P. Barnak

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/66545 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7833 ,  Y10S438/926

摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

摘要翻译： 至少p型和n型半导体器件沉积在包含金属或金属合金栅极的半导体晶片上。 更具体地，在具有n型和p型金属栅极的半导体晶片上形成互补金属氧化物半导体（CMOS）器件。