公开(公告)号：US4894791A

公开(公告)日：1990-01-16

申请号：US828230

申请日：1986-02-10

Applicant: Ching-Lin Jiang ,  William J. Podkowa

Inventor： Ching-Lin Jiang ,  William J. Podkowa

IPC: H03K5/04 ,  H03K19/003

CPC classification number: H03K5/04 ,  H03K19/00323

Abstract: A delay circuit that can be implemented in a monolithic integrated circuit includes a plurality of capacitor/laser-fusible link series pairs. Delay of a binary output signal of the circuit with respect to an input transition is directly proportional to the amount of capacitance connected into the circuit. Because the laser-fusible links can selectively be opened with a laser, the amount of capacitance connected into the circuit can incrementally be reduced; thus, the delay of the circuit is reducibly adjustable to a desired value. By including a plurality of conductive element/laser-fusible link series pairs in the delay circuit, the delay of the circuit is also increasingly adjustable. A method for economically adjusting the delay of each of many like delay circuits embodied in a semiconductor wafer includes measuring a sample of the delays of the delay circuits, calculating an average delay, determining the difference between a desired delay and the average delay to determine an incremental amount of delay to eliminate or to add, determining from predetermined data which fusible links should be opened, and using a laser beam to open the appropriate links.

Abstract translation: 可以在单片集成电路中实现的延迟电路包括多个电容器/激光可熔链节串联对。 相对于输入跃迁的电路的二进制输出信号的延迟与连接到电路中的电容量成正比。 因为激光熔丝可以选择性地用激光打开，连接到电路中的电容量可以逐渐减小; 因此，电路的延迟可以可调节到期望的值。 通过在延迟电路中包括多个导电元件/激光可熔链节串联对，电路的延迟也越来越可调。 用于经济地调节在半导体晶片中实现的许多类似延迟电路中的每一个的延迟的方法包括测量延迟电路的延迟的样本，计算平均延迟，确定期望延迟和平均延迟之间的差以确定 消除或添加的增量的延迟量，从预定数据确定哪个可熔断链接应该被打开，以及使用激光束打开适当的链接。

公开(公告)号：US4545035A

公开(公告)日：1985-10-01

申请号：US400171

申请日：1982-07-20

Applicant: Daniel C. Guterman ,  Ching-Lin Jiang

Inventor： Daniel C. Guterman ,  Ching-Lin Jiang

IPC: G11C14/00 ,  H01L27/108 ,  G11C11/40

CPC classification number: H01L27/108 ,  G11C14/00

Abstract: A compact memory cell combines a volatile dynamic storage section with a shadow nonvolatile section in two vertically stacked element arrays.

Abstract translation: 紧凑型存储单元将易失性动态存储部分与两个垂直堆叠的元件阵列中的阴影非易失部分组合。

公开(公告)号：US4360903A

公开(公告)日：1982-11-23

申请号：US265994

申请日：1980-09-10

Applicant: Robert S. Plachno ,  Ching-Lin Jiang

Inventor： Robert S. Plachno ,  Ching-Lin Jiang

IPC: G11C11/406 ,  G11C11/4063 ,  G11C7/00

CPC classification number: G11C11/406 ,  G11C11/4063

Abstract: A clocking system for a self-refreshed dynamic memory (10) for reading data stored in a memory cell (30) and including clocking circuitry (68) includes detecting changes in an address signal (60). The method further includes generating a memory refresh signal (64, 66) in response to detecting changes in the address signal (60). The memory refresh signal (66) is applied to the semiconductor memory circuit (30) for refreshing data stored in the memory cells of the semiconductor memory circuit (30). After the application of the memory refresh signal (66) to the semiconductor memory circuit (30) the address signal (16) is applied to the semiconductor memory circuit (30) for accessing the addressed memory cell to thereby read the data stored therein. The clocking circuitry (68) is reset and precharged during the application of the refresh signal (66) to the semiconductor memory circuit (30).

Abstract translation: PCT No.PCT / US80 / 01162 Sec。 371日期1980年9月10日 102（e）1980年9月10日PCT PCT日期为1980年9月10日PCT公布。 第WO82 / 00915号公报 日期：1982年3月18日。一种用于读取存储在存储单元（30）中并包括时钟电路（68）的数据的自动刷新动态存储器（10）的计时系统，包括检测地址信号（60）中的变化。 该方法还包括响应于检测到地址信号（60）中的变化而产生存储器刷新信号（64,66）。 存储器刷新信号（66）被施加到半导体存储器电路（30），用于刷新存储在半导体存储器电路（30）的存储单元中的数据。 在向半导体存储器电路（30）施加存储器刷新信号（66）之后，将地址信号（16）施加到半导体存储器电路（30），以访问所寻址的存储器单元，从而读取存储在其中的数据。 在刷新信号（66）施加到半导体存储器电路（30）期间，时钟电路（68）被复位并被预充电。

公开(公告)号：US5351208A

公开(公告)日：1994-09-27

申请号：US874489

申请日：1992-04-27

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: G11C15/04 ,  G11C15/00

CPC classification number: G11C15/04

Abstract: A content addressable memory is provided that includes a memory cell and a first plurality of lines connected directly to the gates of access transistors to this memory cell. These access transistors are further connected to a second plurality of lines. The first and second plurality of lines each perform different functions during read, write, and comparison modes. In another embodiment of the present invention, p-channel transistors are used for a match transistor and its associated pass transistors.

Abstract translation: 提供了一种内容可寻址存储器，其包括存储单元和直接连接到存储单元的存取晶体管的栅极的第一多条线。 这些存取晶体管进一步连接到第二组线。 第一和第二组线在读，写和比较模式下都执行不同的功能。 在本发明的另一个实施例中，p沟道晶体管用于匹配晶体管及其相关联的传输晶体管。

公开(公告)号：US5299156A

公开(公告)日：1994-03-29

申请号：US542689

申请日：1990-06-25

Applicant: Ching-Lin Jiang ,  Clark R. Williams

Inventor： Ching-Lin Jiang ,  Clark R. Williams

IPC: G06F5/06 ,  G11C8/16 ,  G11C11/41 ,  G11C11/412 ,  G11C19/28 ,  G11C11/419

CPC classification number: G11C11/412 ,  G06F5/065 ,  G11C11/41 ,  G11C19/287 ,  G11C8/16

Abstract: A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.

Abstract translation: 双存储单元存储器包括双存储单元的阵列，每个双存储单元包含第一存储单元和第二存储单元。 第一和第二存储器单元是众所周知的六晶体管静态存储单元，其具有用于将数据直接从每个存储器单元的内部数据节点传送到其对应的互补存储器单元的传输电路，而不需要使用使能晶体管 或与每个双存储单元相关联的位线。

公开(公告)号：US5150079A

公开(公告)日：1992-09-22

申请号：US717238

申请日：1991-06-18

Applicant: Clark R. Williams ,  Ching-Lin Jiang

Inventor： Clark R. Williams ,  Ching-Lin Jiang

IPC: H03B5/36

CPC classification number: H03B5/364 ,  H03B2200/0012

Abstract: A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during start-up.

Abstract translation: 一种低功率晶体控制CMOS振荡器，其中在输出放大器的第一级提供长而宽的附加晶体管。 这可以防止输出放大器在启动期间从初级放大器级转移太多的电流。

公开(公告)号：US4871982A

公开(公告)日：1989-10-03

申请号：US264193

申请日：1988-10-28

Applicant: Clark R. Williams ,  Ching-Lin Jiang

Inventor： Clark R. Williams ,  Ching-Lin Jiang

IPC: H03K3/014 ,  H03K3/354 ,  H03L3/00

CPC classification number: H03B5/30 ,  H03B5/06 ,  H03K3/014 ,  H03K3/3545 ,  H03L3/00

Abstract: A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during start-up.

Abstract translation: 一种低功率晶体控制CMOS振荡器，其中在输出放大器的第一级提供长而宽的附加晶体管。 这可以防止输出放大器在启动期间从初级放大器级转移太多的电流。

公开(公告)号：US4460978A

公开(公告)日：1984-07-17

申请号：US322915

申请日：1981-11-19

Applicant: Ching-Lin Jiang ,  David L. Taylor

Inventor： Ching-Lin Jiang ,  David L. Taylor

IPC: G11C14/00 ,  G11C11/40

CPC classification number: G11C14/00

Abstract: A nonvolatile static random access memory cell (10) includes a pair of cross-coupled transistors (12, 14) which function as a bistable circuit to store data states. Variable threshold transistors (36, 41) are respectively connected in series between the driver transistors (12, 14) and load devices (48, 50). A control node (40) is driven to a high voltage state to cause one of the variable threshold transistors (36, 41) to be driven to have a higher threshold voltage and thereby store the data state held in the cross-coupled transistors (12, 14). The data state is thus stored in nonvolatile form. Upon recall the memory cell (10) is reactivated and the threshold differential between the variable threshold transistors (36, 41) causes the driver transistors (12, 14) to be set at the stored data state. The data recalled by the memory cell (10) is in true rather than in complementary form. The variable threshold transistors (36, 41) are reset by driving the power terminal V.sub.cc to a high voltage state to reestablish common threshold voltages for the variable threshold voltage transistors (36, 41).

Abstract translation: 非易失性静态随机存取存储单元（10）包括一对交叉耦合晶体管（12,14），其作为双稳态电路来存储数据状态。 可变阈值晶体管（36,41）分别串联连接在驱动晶体管（12,14）和负载装置（48,50）之间。 控制节点（40）被驱动到高电压状态以使可变阈值晶体管（36,41）中的一个被驱动以具有较高的阈值电压，从而存储保持在交叉耦合晶体管（12）中的数据状态 ，14）。 数据状态因此以非易失性形式存储。 一旦召回，存储器单元（10）被重新激活，并且可变阈值晶体管（36,41）之间的阈值差使得驱动晶体管（12,14）被设置在存储的数据状态。 由存储器单元（10）调用的数据是真实的而不是互补形式。 通过将电源端子Vcc驱动到高电压状态来重建可变阈值晶体管（36,41），以重建可变阈值电压晶体管（36,41）的公共阈值电压。

公开(公告)号：US4308594A

公开(公告)日：1981-12-29

申请号：US117223

申请日：1980-01-31

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: G11C11/41 ,  G11C11/34 ,  G11C11/402 ,  G11C11/412 ,  H01L27/108 ,  H01L29/78 ,  H03K3/356 ,  G11C11/40 ,  G11C11/24

CPC classification number: G11C11/412 ,  G11C11/4023 ,  H01L27/108 ,  H03K3/35606 ,  H03K3/356086

Abstract: An integrated circuit memory cell (10) having a bit line (12), a word line (14) and a cell voltage supply (26) is provided. The integrated circuit memory cell (10) includes a first clock line (34) and a second clock line (36). A first transistor (20) is interconnected to the bit line (12) and the word line (14) for providing access to the memory cell (10). A second transistor (22) is interconnected to the cell voltage supply source (26) and to the first transistor (20) thereby defining a first node (S). The second transistor (22) provides a charging path from the cell voltage supply source (26) to the first node (S). A capacitor (30) is provided and interconnects the first clock line (34) and the second transistor (22). The interconnection between the capacitor (30) and the second transistor (22) defines a second node (K). The capacitor (30) provides a coupling path between the first clock line (34) and the second node (K) for conditionally supplying a voltage from the first clock line (34) to the second node (K) to render voltage at the second node (K) higher than the cell voltage supply source (26). A third transistor is provided for the memory cell (10) and is interconnected to the first node (S) and the second node (K) and the second clock line (36). The third transistor (24) provides a charging path between the second clock line (36) and the second node (K) for conditionally maintaining a voltage at the second node (K).

Abstract translation: 提供具有位线（12），字线（14）和单元电压供应（26）的集成电路存储单元（10）。 集成电路存储单元（10）包括第一时钟线（34）和第二时钟线（36）。 第一晶体管（20）互连到位线（12）和字线（14），用于提供对存储单元（10）的访问。 第二晶体管（22）与电池电压源（26）和第一晶体管（20）互连，由此限定第一节点（S）。 第二晶体管（22）提供从单电池电压源（26）到第一节点（S）的充电路径。 提供电容器（30）并将第一时钟线（34）和第二晶体管（22）互连。 电容器（30）和第二晶体管（22）之间的互连限定第二节点（K）。 电容器（30）在第一时钟线（34）和第二节点（K）之间提供耦合路径，用于从第一时钟线（34）向第二节点（K）有条件地提供电压以在第二时钟线 （K）高于电池电压源（26）。 第三晶体管被提供给存储单元（10）并且互连到第一节点（S）和第二节点（K）和第二时钟线（36）。 第三晶体管（24）在第二时钟线（36）和第二节点（K）之间提供充电路径，用于有条件地维持第二节点（K）的电压。

公开(公告)号：US6118690A

公开(公告)日：2000-09-12

申请号：US563152

申请日：1995-11-27

Applicant: Ching-Lin Jiang ,  Clark R. Williams

Inventor： Ching-Lin Jiang ,  Clark R. Williams

IPC: G06F5/06 ,  G11C8/16 ,  G11C11/41 ,  G11C11/412 ,  G11C19/28 ,  G11C11/419

CPC classification number: G06F5/065 ,  G11C11/41 ,  G11C11/412 ,  G11C19/287 ,  G11C8/16

Abstract: A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.

Abstract translation: 双存储单元存储器包括双存储单元的阵列，每个双存储单元包含第一存储单元和第二存储单元。 第一和第二存储器单元是众所周知的六晶体管静态存储单元，其具有用于将数据直接从每个存储器单元的内部数据节点传送到其对应的互补存储器单元的传输电路，而不需要使用使能晶体管 或与每个双存储单元相关联的位线。