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    Method to form damascene interconnects with sidewall passivation to protect organic dielectrics
    12.
    发明授权
    Method to form damascene interconnects with sidewall passivation to protect organic dielectrics 有权
    形成具有侧壁钝化的镶嵌互连以保护有机电介质的方法

    公开(公告)号：US06358842B1

    公开(公告)日：2002-03-19

    申请号：US09633770

    申请日：2000-08-07

    申请人： Mei-Sheng Zhou ,  Simon Chooi ,  Yi Xu

    发明人： Mei-Sheng Zhou ,  Simon Chooi ,  Yi Xu

    IPC分类号： H01L213205

    CPC分类号： H01L21/76831 ,  H01L21/31138 ,  H01L21/76808

    摘要： A new method of forming a damascene interconnect in the manufacture of an integrated circuit device has been achieved. The damascene interconnect may be a single damascene or a dual damascene. Copper conductors are provided overlying a semiconductor substrate. A first passivation layer is provided overlying the copper conductors. A low dielectric constant layer is deposited overlying the first passivation layer. An optional capping layer is deposited overlying the low dielectric constant layer. A photoresist layer is deposited overlying the capping layer. The capping layer and the low dielectric constant layer are etched through to form via openings. The photoresist layer is simultaneously stripped away while forming a sidewall passivation layer on the sidewalls of the via openings using a sulfur-containing gas. Sidewall bowing and via poisoning are thereby prevented. The first passivation layer is etched through to expose the underlying copper conductors. A copper layer is deposited overlying the capping layer and filling the via openings. The copper layer is polished down to complete the damascene interconnects in the manufacture of the integrated circuit device.

    摘要翻译： 已经实现了在集成电路器件的制造中形成镶嵌互连的新方法。 镶嵌互连可以是单镶嵌或双镶嵌。 提供铜导体覆盖在半导体衬底上。 第一钝化层被提供在铜导体上。 沉积在第一钝化层上的低介电常数层。 沉积覆盖在低介电常数层上的可选的覆盖层。 沉积在覆盖层上的光致抗蚀剂层。 覆盖层和低介电常数层被蚀刻通过以形成通孔。 同时剥离光致抗蚀剂层，同时使用含硫气体在通路孔的侧壁上形成侧壁钝化层。 从而防止侧壁弯曲和通过中毒。 蚀刻第一钝化层以暴露下面的铜导体。 沉积覆盖覆盖层并填充通孔的铜层。 铜层被抛光以在集成电路器件的制造中完成镶嵌互连。

    Integration of silicon-rich material in the self-aligned via approach of dual damascene interconnects
    13.
    发明授权
    Integration of silicon-rich material in the self-aligned via approach of dual damascene interconnects 失效
    将富硅材料集成在双镶嵌互连的自对准通孔中

    公开(公告)号：US06350675B1

    公开(公告)日：2002-02-26

    申请号：US09686282

    申请日：2000-10-12

    申请人： Simon Chooi ,  Mei-Sheng Zhou ,  Subhash Gupta ,  Yi Xu

    发明人： Simon Chooi ,  Mei-Sheng Zhou ,  Subhash Gupta ,  Yi Xu

    IPC分类号： H01L214763

    CPC分类号： H01L21/76832 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826

    摘要： This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, in the formation of self-aligned dual damascene interconnects and vias, which incorporates low dielectric constant intermetal dielectrics (IMD) and utilizes silylated top surface imaging (TSI) photoresist, with a single or multi-step selective reactive ion etch (RIE) process, to form trench/via opening. The invention incorporates the use of a silylated top surface imaging (TSI) resist etch barrier layer to form the via pattern, in the first level of a dual damascene process. Two variations of using the top surface imaging (TSI) resist, with and without leaving an exposed region in place, are described in the first and second embodiment of the invention, and in addition, a thin dielectric layer is made use of just below the resist layer. Provided adhesion between the top surface imaging (TSI) photoresist and the low dielectric constant intermetal dielectric (IMD) is good, the thin dielectric layer described above can be omitted, yielding the third and fourth embodiment of the invention. Special attention in the process is given to protecting the integrity of the low dielectric constant intermetal dielectric (ILD) material, selected from the group consisting of organic based or carbon doped silicon dioxide.

    摘要翻译： 本发明涉及用于半导体集成电路器件的制造方法，更具体地说，涉及形成自对准的双镶嵌互连和通孔，其结合了低介电常数金属间电介质（IMD）并利用甲硅烷基化的顶表面成像（TSI ）光致抗蚀剂，具有单步或多步选择性反应离子蚀刻（RIE）工艺，以形成沟槽/通孔。 本发明包括在双镶嵌工艺的第一水平中使用甲硅烷基化的顶表面成像（TSI）抗蚀剂蚀刻阻挡层以形成通孔图案。 在本发明的第一和第二实施例中描述了使用顶表面成像（TSI）抗蚀剂的两种变型，其具有和不具有将暴露区域保持在适当位置，此外，使用刚好低于 抗蚀剂层。 提供顶表面成像（TSI）光致抗蚀剂和低介电常数金属间电介质（IMD）之间的粘附性是好的，可以省略上述薄介电层，产生本发明的第三和第四实施例。 该方法中特别注意保护低介电常数金属间电介质（ILD）材料的完整性，该材料选自有机基或掺碳二氧化硅。

    MULTI-ZONE CARRIER HEAD FOR CHEMICAL MECHANICAL POLISHING AND CMP METHOD THEREOF
    14.
    发明申请
    MULTI-ZONE CARRIER HEAD FOR CHEMICAL MECHANICAL POLISHING AND CMP METHOD THEREOF 审中-公开
    用于化学机械抛光的多区域载体头及其CMP方法

    公开(公告)号：US20070167110A1

    公开(公告)日：2007-07-19

    申请号：US11306913

    申请日：2006-01-16

    申请人： Yu-Hsiang Tseng ,  Kai-Hung Alex See ,  Mei-Sheng Zhou ,  Jin Yu ,  Zheng Zou ,  Wen-Zhan Zhou

    发明人： Yu-Hsiang Tseng ,  Kai-Hung Alex See ,  Mei-Sheng Zhou ,  Jin Yu ,  Zheng Zou ,  Wen-Zhan Zhou

    IPC分类号： B24B51/00

    CPC分类号： B24B37/30

    摘要： A multi-zone carrier head includes a housing; a retaining ring secured to a lower edge of the housing; a backing plate having a plurality of non-concentric pressure zones defined by a plurality of isolated apertures on the backing plate; wherein the backing plate has a wafer side and a non-wafer side, the wafer side facing a backside of a wafer during a CMP operation; and a plurality of pneumatic bladder for independently controlling pressure exerted in the respective non-concentric pressure zones on the backside of the wafer during the CMP operation.

    摘要翻译： 多区域承载头包括壳体; 保持环固定到壳体的下边缘; 背板，其具有由背板上的多个隔离孔限定的多个非同心压力区; 其中所述背板具有晶片侧和非晶片侧，所述晶片侧在CMP操作期间面向晶片的背面; 以及多个气囊，用于在CMP操作期间独立地控制施加在晶片背面上的各个非同心压力区中的压力。

    System and method for dry chamber temperature control
    16.
    发明申请
    System and method for dry chamber temperature control 审中-公开
    干室温度控制系统和方法

    公开(公告)号：US20050016467A1

    公开(公告)日：2005-01-27

    申请号：US10626998

    申请日：2003-07-24

    申请人： Yi-Li Hsiao ,  Mei-Sheng Zhou ,  Chin-Hsin Peng ,  Chien-Ling Huang ,  Tse-Yi Chen ,  Chun-Yi Lee ,  Hsueh-Chang Wu

    发明人： Yi-Li Hsiao ,  Mei-Sheng Zhou ,  Chin-Hsin Peng ,  Chien-Ling Huang ,  Tse-Yi Chen ,  Chun-Yi Lee ,  Hsueh-Chang Wu

    IPC分类号： C23C16/00 ,  H01L21/00

    CPC分类号： H01L21/67248 ,  H01J2237/2001 ,  H01L21/67109

    摘要： A system and method which is capable of compensating for unintended elevations in process temperatures induced in a substrate during a semiconductor fabrication process in order to reduce or eliminate disparities in critical dimensions of device features. The system may be a plasma etching system comprising a process chamber containing an electrostatic chuck (ESC) for supporting a wafer substrate. A chiller outside the process chamber includes a main coolant chamber, which contains a main coolant fluid, as well as an compensation coolant chamber, which contains an compensation coolant fluid. A main circulation loop normally circulates the main coolant fluid from the main coolant chamber through the electrostatic chuck to maintain the chuck at a desired set point temperature.

    摘要翻译： 一种系统和方法，其能够在半导体制造过程期间补偿在衬底中感应的工艺温度中的意外高度，以便减少或消除器件特征的关键尺寸的不均匀性。 该系统可以是包括含有用于支撑晶片衬底的静电吸盘（ESC）的处理室的等离子体蚀刻系统。 处理室外部的冷却器包括主冷却剂室，其包含主冷却剂流体，以及补偿冷却剂室，其包含补偿冷却剂流体。 主循环回路通常使主冷却剂流体从主冷却剂室通过静电吸盘循环，以将卡盘保持在所需的设定点温度。

    Methods to form dual metal gates by incorporating metals and their conductive oxides
    17.
    发明授权
    Methods to form dual metal gates by incorporating metals and their conductive oxides 失效
    通过引入金属及其导电氧化物形成双金属栅极的方法

    公开(公告)号：US06835989B2

    公开(公告)日：2004-12-28

    申请号：US10736943

    申请日：2003-12-16

    申请人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

    发明人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

    IPC分类号： H01L2976

    CPC分类号： H01L21/823842 ,  H01L29/66545

    摘要： Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are oxygen implanted and oxidized. The PMOS gate has the higher work function.

    摘要翻译： 描述形成双金属栅极CMOS晶体管的方法。 半导体衬底的NMOS和PMOS有源区由隔离区隔开。 金属层沉积在每个有源区域中的栅极电介质层上。 将氧离子注入到一个活性区域中的金属层中，以形成被氧化形成金属氧化物层的注入金属层。 此后，金属层和金属氧化物层被图案化以在一个有源区域中形成金属栅极，而在另一个有源区域中形成金属氧化物栅极，其中具有较高功函数的栅极的有源区是PMOS有源区。 或者，两个栅极可以是金属氧化物栅极，其中两个栅极的氧化物浓度不同。 或者，可以在每个有源区域中形成伪栅极并且被电介质层覆盖。 介电层被平坦化，从而暴露虚拟栅极。 去除虚拟栅极留下栅极开口到半导体衬底。 金属层沉积在栅极开口内的栅极电介质层上，形成金属栅极。 一个或两个栅极是氧注入和氧化的。 PMOS栅极具有较高的功函数。

    Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask
    18.
    发明授权
    Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask 有权
    通过使用自对准反向间隔件作为硬掩模形成小晶体管栅极的方法

    公开(公告)号：US06610604B1

    公开(公告)日：2003-08-26

    申请号：US10068053

    申请日：2002-02-05

    申请人： Chew-Hoe Ang ,  Eng-Hua Lim ,  Randall Cha ,  Jia-Zhen Zheng ,  Elgin Quek ,  Mei-Sheng Zhou ,  Daniel Yen

    发明人： Chew-Hoe Ang ,  Eng-Hua Lim ,  Randall Cha ,  Jia-Zhen Zheng ,  Elgin Quek ,  Mei-Sheng Zhou ,  Daniel Yen

    IPC分类号： H01L21302

    CPC分类号： H01L21/28132

    摘要： A method of forming narrow gates comprising the following steps. A substrate is provided having an overlying Si3N4 or an SiO2/Si3N4 stack gate dielectric layer. A gate material layer is formed over the gate dielectric layer. A hard mask layer is formed over the gate material layer. The hard mask layer and the gate material layer are patterned to form a hard mask/gate material layer stack. A planarized dielectric layer is formed surrounding the hard mask/gate material layer stack. The patterned hard mask layer is removed from over the patterned gate material layer to form a cavity having exposed dielectric layer side walls. Masking spacers are formed on the exposed dielectric layer side walls over a portion of the patterned gate material layer. The patterned gate material layer is etched using the masking spacers as masks to expose a portion of the gate dielectric layer. The planarized dielectric layer is removed. The masking spacers are removed to form narrow gates comprising gate material.

    摘要翻译： 一种形成窄门的方法，包括以下步骤。 提供具有覆盖的Si 3 N 4或SiO 2 / Si 3 N 4堆叠栅极介电层的衬底。 栅极材料层形成在栅极介电层上。 在栅极材料层上形成硬掩模层。 图案化硬掩模层和栅极材料层以形成硬掩模/栅极材料层堆叠。 形成围绕硬掩模/栅极材料层叠层的平坦化介电层。 图案化的硬掩模层从图案化的栅极材料层上去除以形成具有暴露的电介质层侧壁的空腔。 屏蔽间隔物形成在图案化栅极材料层的一部分上的暴露的电介质层侧壁上。 使用掩模间隔物作为掩模蚀刻图案化的栅极材料层，以露出栅极电介质层的一部分。 去除平坦化的介电层。 去除掩模间隔物以形成包括栅极材料的窄门。

    Dual metal gate process: metals and their silicides
    19.
    发明授权
    Dual metal gate process: metals and their silicides 有权
    双金属栅极工艺：金属及其硅化物

    公开(公告)号：US06475908B1

    公开(公告)日：2002-11-05

    申请号：US09981415

    申请日：2001-10-18

    申请人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

    发明人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

    IPC分类号： H01L2144

    CPC分类号： H01L29/66545 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/517

    摘要： Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are silicon implanted and silicided. The PMOS gate has the higher work function.

    摘要翻译： 描述形成双金属栅极CMOS晶体管的方法。 半导体衬底的NMOS和PMOS有源区由隔离区隔开。 金属层沉积在每个有源区域中的栅极电介质层上。 将硅离子注入到一个有源区域中的金属层中以形成硅化物以形成金属硅化物层的注入金属层。 此后，金属层和金属硅化物层被图案化以在一个有源区域中形成金属栅极，在另一个有源区域中形成金属硅化物栅极，其中具有较高功函数的栅极的有源区是PMOS有源区。 或者，两个栅极可以是金属硅化物栅极，其中两个栅极的硅浓度不同。 或者，可以在每个有源区域中形成伪栅极并且被电介质层覆盖。 介电层被平坦化，从而暴露虚拟栅极。 去除虚拟栅极留下栅极开口到半导体衬底。 金属层沉积在栅极开口内的栅极电介质层上，形成金属栅极。 一个或两个栅极是硅植入和硅化的。 PMOS栅极具有较高的功函数。