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56 条记录 (耗时 0.043 秒)

    Darc layer for MIM process integration
    13.
    发明授权
    Darc layer for MIM process integration 有权
    用于MIM工艺集成的Darc层

    公开(公告)号：US06576526B2

    公开(公告)日：2003-06-10

    申请号：US09900398

    申请日：2001-07-09

    申请人： Shao Kai ,  Wu-Guan Ping ,  Chen Liang ,  Cheng-Wei Hua ,  Sanford Chu ,  Daniel Yen

    发明人： Shao Kai ,  Wu-Guan Ping ,  Chen Liang ,  Cheng-Wei Hua ,  Sanford Chu ,  Daniel Yen

    IPC分类号： H01L2120

    CPC分类号： H01L28/55 ,  H01L21/31122 ,  H01L21/32136

    摘要： A new processing sequence is provided for the creation of a MIM capacitor. The process starts with the deposition of a first layer of metal. Next are deposited listed, a thin layer of metal, a layer of insulation, a second layer of metal and a layer of Anti Reflective Coating. An etch is then performed to form the second electrode of the MIM capacitor (using the etch stop layer to stop this etch), MIM spacers are formed on the sidewalls of the second electrode of the MIM capacitor (also using the etch stop layer to stop this etch). The dielectric and first electrode of the MIM capacitor are formed by etching through the second layer of insulation and the first layer of metal. This is followed by conventional processing to create contact points to the MIM capacitor.

    摘要翻译： 为MIM电容器的创建提供了新的处理顺序。 该过程开始于沉积第一层金属。 接下来是沉积列表，薄层金属，一层绝缘层，第二层金属和一层抗反射涂层。 然后进行蚀刻以形成MIM电容器的第二电极（使用蚀刻停止层来停止该蚀刻），MIM间隔物形成在MIM电容器的第二电极的侧壁上（也使用蚀刻停止层停止 这个蚀刻）。 MIM电容器的电介质和第一电极通过蚀刻穿过第二绝缘层和第一金属层而形成。 接下来是常规处理以产生与MIM电容器的接触点。

    Method for forming a MIM (metal-insulator-metal) capacitor
    14.
    发明授权
    Method for forming a MIM (metal-insulator-metal) capacitor 有权
    用于形成MIM（金属 - 绝缘体 - 金属）电容器的方法

    公开(公告)号：US06780727B2

    公开(公告)日：2004-08-24

    申请号：US10132244

    申请日：2002-04-25

    申请人： Ng Chit Hwei ,  Shao Kai ,  Bao Guang Wen ,  Tjoa Tjin Tjin ,  Sanford Chu

    发明人： Ng Chit Hwei ,  Shao Kai ,  Bao Guang Wen ,  Tjoa Tjin Tjin ,  Sanford Chu

    IPC分类号： H01L218242

    CPC分类号： H01L28/60 ,  H01L21/0276 ,  H01L21/32139 ,  H01L27/0805

    摘要： Methods for forming a metal-insulator-metal (MIM) capacitor using an organic anti-reflective coating (ARC) are described. The first electrode of the MIM capacitor is formed from a first metal layer. The organic ARC is applied, and the second electrode of the MIM capacitor is formed from a second metal layer. The organic ARC is then removed using a nominal clean technique. Because the organic ARC is removed, the performance of the MIM capacitor is improved. Specifically, the breakdown voltage of the MIM capacitor increases and the leakage current decreases.

    摘要翻译： 描述了使用有机抗反射涂层（ARC）形成金属 - 绝缘体 - 金属（MIM）电容器的方法。 MIM电容器的第一电极由第一金属层形成。 施加有机ARC，并且MIM电容器的第二电极由第二金属层形成。 然后使用标称清洁技术除去有机ARC。 由于去除了有机ARC，因此提高了MIM电容器的性能。 具体地说，MIM电容器的击穿电压增加，漏电流减小。

    Metal sandwich structure for MIM capacitor onto dual damascene
    15.
    发明授权
    Metal sandwich structure for MIM capacitor onto dual damascene 有权
    金属夹层结构MIM电容器到双镶嵌

    公开(公告)号：US06746914B2

    公开(公告)日：2004-06-08

    申请号：US10140644

    申请日：2002-05-07

    申请人： Shao Kai ,  Ng Hwei ,  Sanford Chu

    发明人： Shao Kai ,  Ng Hwei ,  Sanford Chu

    IPC分类号： H01L218242

    CPC分类号： H01L28/40 ,  H01L21/76838 ,  H01L28/60

    摘要： A first and second damascene copper interconnect plug are created over the surface of a substrate. A MIM capacitor, which is aligned with the second damascene copper interconnect plug, is created by a one-time etch of a stack of layers comprising Ta/capacitor dielectric/Ta. Copper interconnects are then created aligned with the MIM capacitor and the second damascene interconnect plug.

    摘要翻译： 在衬底的表面上形成第一和第二镶嵌铜互连插头。 与第二镶嵌铜互连插塞对准的MIM电容器通过一次蚀刻包括Ta /电容器电介质/ Ta的层的叠层来产生。 然后，与MIM电容器和第二镶嵌互连插头对准铜互连。

    HIGH PERFORMANCE LDMOS DEVICE HAVING ENHANCED DIELECTRIC STRAIN LAYER
    17.
    发明申请
    HIGH PERFORMANCE LDMOS DEVICE HAVING ENHANCED DIELECTRIC STRAIN LAYER 有权
    具有增强型电介质层的高性能LDMOS器件

    公开(公告)号：US20120119293A1

    公开(公告)日：2012-05-17

    申请号：US13333118

    申请日：2011-12-21

    申请人： Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Verma Purakh

    发明人： Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Verma Purakh

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7835 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/7846

    摘要： An LDMOS device includes a substrate having a surface and a gate electrode overlying the surface and defining a channel region in the substrate below the gate electrode. A drain region is spaced apart from the channel region by an isolation region. The isolation region includes a region of high tensile stress and is configured to induce localized stress in the substrate in close proximity to the drain region. The region of high tensile stress in the isolation region can be formed by high-stress silicon oxide or high-stress silicon nitride. In a preferred embodiment, the isolation region is a shallow trench isolation region formed in the substrate intermediate to the gate electrode and the drain region.

    摘要翻译： LDMOS器件包括具有表面的衬底和覆盖该表面的栅电极，并且在栅电极下方的衬底中限定沟道区。 漏极区域与沟道区域隔开隔离区域。 隔离区域包括高拉伸应力的区域，并且被配置为在靠近漏极区域的基板中引起局部应力。 隔离区域中的高拉伸应力的区域可以由高应力氧化硅或高应力氮化硅形成。 在优选实施例中，隔离区是形成在栅极电极和漏极区域中间的衬底中的浅沟槽隔离区。

    Semiconductor structure including high voltage device
    19.
    发明授权
    Semiconductor structure including high voltage device 有权
    半导体结构包括高压器件

    公开(公告)号：US07867862B2

    公开(公告)日：2011-01-11

    申请号：US11855168

    申请日：2007-09-14

    申请人： Jeoung Mo Koo ,  Purakh Raj Verma ,  Sanford Chu ,  Chunlin Zhu ,  Yisuo Li

    发明人： Jeoung Mo Koo ,  Purakh Raj Verma ,  Sanford Chu ,  Chunlin Zhu ,  Yisuo Li

    IPC分类号： H01L21/335

    CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/66568 ,  H01L29/7833

    摘要： A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first side of the gate stack. A first isolation structure in the substrate, located on the first side of the gate stack, separates the channel and the first diffusion region. The high voltage device also includes a first drift region in the substrate coupling the channel to the first diffusion region, wherein the first drift region comprises a non-uniform depth profile conforming to a profile of the first isolation structure.

    摘要翻译： 高压器件包括其上限定有器件区域的衬底。 栅极堆叠设置在器件区域中的衬底上。 沟道区域位于栅堆叠下方的衬底中，而第一扩散区位于栅层叠的第一侧上的衬底中。 位于栅极堆叠的第一侧的衬底中的第一隔离结构分离通道和第一扩散区域。 高电压装置还包括在衬底中的第一漂移区域，其将沟道耦合到第一扩散区域，其中第一漂移区域包括符合第一隔离结构的轮廓的不均匀的深度分布。

    Silicon-based inductor with varying metal-to-metal conductor spacing
    20.
    发明授权
    Silicon-based inductor with varying metal-to-metal conductor spacing 失效
    具有不同金属 - 金属导体间距的硅基电感器

    公开(公告)号：US06714112B2

    公开(公告)日：2004-03-30

    申请号：US10144542

    申请日：2002-05-10

    申请人： Sia Choon Beng ,  Yeo Kiat Seng ,  Sanford Chu

    发明人： Sia Choon Beng ,  Yeo Kiat Seng ,  Sanford Chu

    IPC分类号： H01F500

    CPC分类号： H01F17/0006 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A silicon-based inductor in a semiconductor is disclosed. One embodiment provides for an inductor having a metal region comprising turns. The metal region has spacing between adjacent turns. The width of the spacing varies. The spacing is pre-determined to optimize the performance of the inductor by reducing eddy currents in the turns and reducing eddy currents induced in a substrate. One embodiment provides for an inductor having a spiral structure. The spiral structure may have a number of turns with the spacing between the turns of the inductor being larger near the inside of the spiral structure. A large spacing between the inductor's inner turns may serve to reduce both conductor eddy currents and the induced substrate current. Thus, the structure improves the inductor's overall performance.

    摘要翻译： 公开了半导体中的硅基电感器。 一个实施例提供了具有包括匝的金属区域的电感器。 金属区域在相邻的匝之间具有间隔。 间距的宽度变化。 通过减小匝中的涡电流并减少在衬底中感应的涡电流，预先确定间距以优化电感器的性能。 一个实施例提供具有螺旋结构的电感器。 螺旋结构可以具有多个匝数，在螺旋结构的内部附近，电感器匝之间的间距更大。 电感器内圈之间的大间距可用于减少导体涡流和感应衬底电流。 因此，该结构提高了电感器的整体性能。