公开(公告)号：US08329530B1

公开(公告)日：2012-12-11

申请号：US13566741

申请日：2012-08-03

申请人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

发明人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L27/11521 ,  H01L21/76816 ,  H01L27/115

摘要： A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

摘要翻译： 公开了一种用于在闪速存储器件中提供至少一个触点的方法和系统。 闪速存储器件包括多个栅极堆叠，并且至少包括一个包括多晶硅层作为顶表面的部件。 该方法和系统还包括在多晶硅层的顶表面上形成硅化物，并提供覆盖多个栅叠层，至少一个元件和硅化物的绝缘层。 该方法和系统还包括蚀刻绝缘层以提供至少一个接触孔。 绝缘层蚀刻步骤使用硅化物作为蚀刻停止层，以确保绝缘蚀刻步骤​​不会蚀刻通过多晶硅层。 该方法和系统还包括用导体填充至少一个接触孔。

公开(公告)号：US07439141B2

公开(公告)日：2008-10-21

申请号：US10277395

申请日：2002-10-22

申请人： Unsoon Kim ,  Yu Sun ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Harpreet K. Sachar ,  Mark S. Chang

发明人： Unsoon Kim ,  Yu Sun ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Harpreet K. Sachar ,  Mark S. Chang

IPC分类号： H01L21/00

CPC分类号： H01L21/76235

摘要： A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches into a silicon substrate between active regions, and performing a double liner oxidation process on the trenches. The method further includes performing a double sacrificial oxidation process on the active regions, wherein corners of the trenches are substantially rounded by the four oxidation processes.

摘要翻译： 公开了一种用于在半导体制造期间进行浅沟槽隔离的方法，其改善沟槽角圆化。 该方法包括将沟槽蚀刻到有源区域之间的硅衬底中，并在沟槽上执行双衬层氧化工艺。 该方法还包括对活性区域进行双重牺牲氧化处理，其中沟槽的角通过四个氧化过程基本上被圆化。

公开(公告)号：US06727195B2

公开(公告)日：2004-04-27

申请号：US09777457

申请日：2001-02-06

申请人： Michael K. Templeton ,  Mark S. Chang

发明人： Michael K. Templeton ,  Mark S. Chang

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/76802 ,  H01L23/528 ,  H01L27/115 ,  H01L2924/0002 ,  Y10S438/945 ,  Y10S438/946 ,  Y10S438/947 ,  H01L2924/00

摘要： A method and system for providing a semiconductor device is disclosed. The method and system include providing a semiconductor substrate and providing a plurality of lines separated by a plurality of spaces. Each of the plurality of spaces preferably has a first width that is less than a minimum feature size. In one aspect, the method and system include providing a reverse mask having a plurality of apertures on an insulating layer. In this aspect, the method and system also include trimming the reverse mask to increase a size of each of the plurality of apertures, removing a portion of the insulating layer exposed by the plurality of trimmed apertures to provide a plurality of trenches and providing a plurality of lines in the plurality of trenches. In a second aspect, the method and system include providing a reverse mask on the insulating layer and removing a first portion of the insulating layer exposed by the plurality of apertures to provide a plurality of trenches. The reverse mask includes a plurality of apertures having a first width. Each of the plurality of trenches has a width. In this aspect, the method and system also include trimming a second portion of the insulating layers to increase the width of each of the plurality of trenches and providing a plurality of lines in the plurality of trenches.

摘要翻译： 公开了一种用于提供半导体器件的方法和系统。 该方法和系统包括提供半导体衬底并提供由多个空间隔开的多条线。 多个空间中的每一个优选地具有小于最小特征尺寸的第一宽度。 在一个方面，该方法和系统包括在绝缘层上提供具有多个孔的反向掩模。 在这方面，该方法和系统还包括修整反向掩模以增加多个孔中的每一个的尺寸，去除由多个修剪的孔暴露的绝缘层的一部分以提供多个沟槽并提供多个 的多个沟槽中的线。 在第二方面，所述方法和系统包括在绝缘层上提供反向掩模，并且去除由多个孔暴露的绝缘层的第一部分以提供多个沟槽。 反向掩模包括具有第一宽度的多个孔。 多个沟槽中的每一个具有宽度。 在这方面，该方法和系统还包括修整绝缘层的第二部分以增加多个沟槽中的每一个的宽度并且在多个沟槽中提供多条线。

公开(公告)号：US06509232B1

公开(公告)日：2003-01-21

申请号：US09969573

申请日：2001-10-01

申请人： Unsoon Kim ,  Mark S. Chang ,  Yider Wu ,  Chi Chang ,  Angela Hui ,  Yu Sun

发明人： Unsoon Kim ,  Mark S. Chang ,  Yider Wu ,  Chi Chang ,  Angela Hui ,  Yu Sun

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536

摘要： STI (shallow trench isolation) structures are formed for a flash memory device fabricated within an semiconductor substrate comprised of a core area having an array of core flash memory cells fabricated therein and comprised of a periphery area having logic circuitry fabricated therein. A first set of STI (shallow trench isolation) openings within the core area are etched through the semiconductor substrate, and a second set of STI (shallow trench isolation) openings within the periphery area are etched through the semiconductor substrate. A core active device area of the semiconductor substrate within the core area is surrounded by the first set of STI openings, and a periphery active device area of the semiconductor substrate within the periphery area is surrounded by the second set of STI openings. Dielectric liners are formed at sidewalls of the first and second sets of STI openings with reaction of the semiconductor substrate at the sidewalls of the STI openings such that top corners of the semiconductor substrate of the core and periphery active device areas adjacent the STI openings are rounded. A trench dielectric material is deposited to fill the STI openings. In addition, the top corners of the periphery active device area are exposed by etching portions of the sidewalls of the second set of STI structures in a dip-off etch. The exposed top corners of the periphery active device area are further rounded after additional thermal oxidation of the exposed top corners of the periphery active device area. The rounded corners of the core and periphery active device areas result in minimized leakage current through a flash memory cell fabricated within the core active device area and through a MOSFET fabricated within the periphery active device area.

摘要翻译： 形成STI（浅沟槽隔离）结构，用于制造在半导体衬底内的闪存器件，该半导体衬底由具有在其中制造的核心闪存单元阵列的核心区域组成，并由其中制造的逻辑电路的外围区域组成。 核心区域内的第一组STI（浅沟槽隔离）开口被蚀刻穿过半导体衬底，并且外围区域内的第二组STI（浅沟槽隔离）开口被蚀刻穿过半导体衬底。 核心区域内的半导体衬底的核心有源器件区域由第一组STI开口包围，并且周边区域内的半导体衬底的外围有源器件区域被第二组STI开口包围。 电介质衬垫通过半导体衬底在STI开口的侧壁处的反应而形成在第一和第二组STI开口的侧壁处，使得芯部的半导体衬底和邻近STI开口的周边有源器件区域的顶角是圆形的 。 沉积沟槽电介质材料以填充STI开口。 此外，通过在浸渍蚀刻中蚀刻第二组STI结构的侧壁的部分来暴露外围有源器件区域的顶角。 外围有源器件区域的暴露的顶角在外围有源器件区域的暴露顶角的额外的热氧化之后被进一步倒圆。 核心和外围有源器件区域的圆角导致通过在核心有源器件区域内制造的闪存单元和通过在外围有源器件区域内制造的MOSFET的最小化的漏电流。

公开(公告)号：US06472327B2

公开(公告)日：2002-10-29

申请号：US09925205

申请日：2001-08-08

申请人： King Wai Kelwin Ko ,  Mark S. Chang ,  Hao Fang

发明人： King Wai Kelwin Ko ,  Mark S. Chang ,  Hao Fang

IPC分类号： H01L21304

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/11534

摘要： A method and system for etching gate oxide during transistor fabrication is disclosed. The method and system begin by depositing a gate oxide on a substrate, followed by a deposition of a tunnel oxide mask over a portion of the gate oxide. The method and system further include performing a combination dry/wet-etch to remove the gate oxide uncovered by the tunnel oxide mask, which minimizes tunnel oxide undercut.

摘要翻译： 公开了在晶体管制造期间蚀刻栅极氧化物的方法和系统。 该方法和系统首先通过在衬底上沉积栅极氧化物，然后在栅极氧化物的一部分上沉积隧道氧化物掩模。 该方法和系统还包括执行干/湿蚀刻组合以去除未被隧道氧化物掩模覆盖的栅极氧化物，其使隧道氧化物底切最小化。

公开(公告)号：US06420224B2

公开(公告)日：2002-07-16

申请号：US09836064

申请日：2001-04-16

申请人： Tatsuya Kajita ,  Mark S. Chang

发明人： Tatsuya Kajita ,  Mark S. Chang

IPC分类号： H01L218238

CPC分类号： G03F7/0035 ,  H01L23/544 ,  H01L27/1052 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2223/5448 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor photomask set for producing wafer alignment accuracy in a semiconductor fabrication process. The photomask set produces an alignment mark that is accurate for subsequent fabrication after undergoing a dual field oxide (FOX) fabrication process. Prior arts methods have traditionally covered the alignment marks with layers of oxide material. The method includes the steps of: (a) providing a first photomask member having mask portions for forming a plurality of first field oxide regions on a first region of a semiconductor substrate and also having a mask portion for forming an alignment marker; (b) providing a second photomask member having mask portions for forming a plurality of second field oxide regions on a second region of the semiconductor substrate and also having mask portions delineated for covering any first field oxide regions and alignment marker formed by using the first photomask member; (c) forming the first field oxide regions and the alignment marker utilizing the first photomask member; (d) covering the formed first field oxide regions and the alignment marker with a photoresist material by utilizing the second photomask member; (e) forming the second field oxide regions after utilizing the second photomask member; (f) facilitating wafer alignment accuracy by removing the photoresist material and exposing the alignment marker; and (g) aligning a semiconductor wafer by utilizing the exposed alignment marker. The mask set can be used in conjunction with stepper wafer alignment tools and is especially useful in forming a memory semiconductor product capable of performing block data erasure operations. The exposed alignment marker facilitates checking and testing mask misalignment during the fabrication process.

摘要翻译： 一种用于在半导体制造工艺中产生晶片对准精度的半导体光掩模组。 光掩模组产生对准标记，其在进行双场氧化物（FOX）制造工艺之后的后续制造中是准确的。 现有技术的方法传统上用氧化物材料层覆盖对准标记。 该方法包括以下步骤：（a）提供具有用于在半导体衬底的第一区域上形成多个第一场氧化物区域的掩模部分并且还具有用于形成对准标记的掩模部分的第一光掩模构件; （b）提供具有掩模部分的第二光掩模部件，用于在半导体衬底的第二区域上形成多个第二场氧化物区域，并且还具有描绘用于覆盖任何第一场氧化物区域的掩模部分和使用第一光掩模形成的对准标记 会员; （c）利用第一光掩模构件形成第一场氧化物区域和对准标记; （d）利用第二光掩模件覆盖所形成的第一场氧化物区域和对准标记物与光致抗蚀剂材料; （e）在利用第二光掩模构件之后形成第二场氧化物区域; （f）通过去除光致抗蚀剂材料并暴露对准标记物来促进晶片对准精度; 和（g）通过利用曝光的对准标记对准半导体晶片。 掩模组可与步进晶片对准工具结合使用，并且特别适用于形成能够执行块数据擦除操作的存储器半导体产品。 暴露的对准标记有助于在制造过程中检查和测试掩模未对准。

公开(公告)号：US07361588B2

公开(公告)日：2008-04-22

申请号：US11098049

申请日：2005-04-04

申请人： Phillip L. Jones ,  Mark S. Chang ,  Scott A. Bell

发明人： Phillip L. Jones ,  Mark S. Chang ,  Scott A. Bell

IPC分类号： H01L21/4763

CPC分类号： H01L21/32139 ,  H01L21/3088 ,  H01L21/31144

摘要： A method of reducing critical dimensions of a feature in a anti-reflective coating layer structure can utilize a polymerizing agent. The anti-reflective coating structure can be utilized to form various integrated circuit structures. The anti-reflective coating can be utilized to form gate stacks comprised of polysilicon and a dielectric layer, conductive lines, or other IC structure. The polymerizing agent can include carbon, hydrogen and fluorine.

摘要翻译： 降低抗反射涂层结构中的特征的关键尺寸的方法可以利用聚合剂。 抗反射涂层结构可用于形成各种集成电路结构。 抗反射涂层可用于形成由多晶硅和电介质层，导电线或其它IC结构组成的栅叠层。 聚合剂可以包括碳，氢和氟。

公开(公告)号：US06812077B1

公开(公告)日：2004-11-02

申请号：US10299433

申请日：2002-11-19

申请人： Darin Chan ,  Douglas J. Bonser ,  Mark S. Chang

发明人： Darin Chan ,  Douglas J. Bonser ,  Mark S. Chang

IPC分类号： H01L2100

CPC分类号： H01L21/32105 ,  H01L21/28088 ,  H01L21/28123

摘要： Patterning of a gate line is terminated prior to etching completely through the conductive layer from which it is patterned. Surfaces of the conductive layer are then reacted in a reactive atmosphere, and the reacted surfaces are removed, creating a narrow gate line. The protection provided by the remaining portion of the conductive layer during reaction protects the lower corners of the patterned feature from undercutting growth of reacted material. Alternatively, a gate line is patterned from a multi-layered conductive structure that includes a lower conductive layer and an upper conductive layer that exhibits higher reactivity in a reactive atmosphere than the lower layer. The upper layer is patterned and then the structure is reacted in the reactive atmosphere. Reacted portions of the upper layer are then removed and the lower layer is patterned in a self-aligned manner to complete the formation of a gate line and gate insulator.

摘要翻译： 在蚀刻完全通过图案化的导电层之前终止栅极线的图案化。 然后在反应性气氛中使导电层的表面反应，除去反应的表面，产生窄的栅极线。 在反应期间由导电层的剩余部分提供的保护保护图案化特征的下角部不被反应材料的底切生长。 或者，栅极线从包括下导电层和上导电层的多层导电结构图案化，反应性气氛中的反应性比下层高。 上层被图案化，然后结构在反应性气氛中反应。 然后去除上层的反应部分，并且以自对准方式图案化下层，以完成栅极线和栅极绝缘体的形成。

公开(公告)号：US06750127B1

公开(公告)日：2004-06-15

申请号：US10367407

申请日：2003-02-14

申请人： Mark S. Chang ,  Darin Chan ,  Chih Yuh Yang ,  Lu You ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Douglas J. Bonser

发明人： Mark S. Chang ,  Darin Chan ,  Chih Yuh Yang ,  Lu You ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Douglas J. Bonser

IPC分类号： H01L213205

CPC分类号： H01L21/32139 ,  H01L21/0332 ,  H01L21/0337

摘要： An amorphous carbon layer is implanted with one or more dopants that enhance the etch resistivity of the amorphous carbon to etchants such as chlorine and HBr that are typically used to etch polysilicon. Such a layer may be pattern to form a handmask for etching polysilicon that provides improved pattern transfer accuracy compared to conventional undoped amorphous carbon.

摘要翻译： 注入一个或多个掺杂剂的无定形碳层，其增强无定形碳对通常用于蚀刻多晶硅的蚀刻剂如氯和HBr的蚀刻电阻率。 这样的层可以被图案化以形成用于蚀刻多晶硅的手掩模，其与常规未掺杂的无定形碳相比提供改进的图案转印精度。

公开(公告)号：US06642148B1

公开(公告)日：2003-11-04

申请号：US10126326

申请日：2002-04-19

申请人： Kouros Ghandehari ,  Emmanuil H. Lingunis ,  Mark S. Chang ,  Angela Hui ,  Scott Bell ,  Jusuke Ogura

发明人： Kouros Ghandehari ,  Emmanuil H. Lingunis ,  Mark S. Chang ,  Angela Hui ,  Scott Bell ,  Jusuke Ogura

IPC分类号： H01L21302

CPC分类号： H01L29/6659 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/743 ,  H01L27/112 ,  H01L27/11521 ,  H01L27/11568

摘要： The present invention generally relates to a method of forming a graded junction within a semiconductor substrate. A first masking pattern having a first opening characterized by a first lateral dimension is formed over the semiconductor substrate. The semiconductor substrate is doped with a first dopant, using the first masking pattern as a doping mask, thereby forming a first dopant region in the semiconductor substrate underlying the first opening. The first masking pattern is swelled to decrease the first lateral dimension of the first opening to a second lateral dimension. The semiconductor substrate is then doped with a second dopant, using the swelled first masking pattern as a doping mask, thereby forming a second dopant region in the semiconductor substrate, and furthermore defining a graded junction within the semiconductor substrate.

摘要翻译： 本发明一般涉及一种在半导体衬底内形成渐变结的方法。 在半导体衬底上形成第一掩模图案，其具有由第一横向尺寸表征的第一开口。 半导体衬底掺杂有第一掺杂剂，使用第一掩模图案作为掺杂掩模，由此在第一开口下面的半导体衬底中形成第一掺杂区域。 第一掩模图案被膨胀以将第一开口的第一横向尺寸减小到第二横向尺寸。 然后使用膨胀的第一掩模图案作为掺杂掩模，然后用半导体衬底掺杂第二掺杂剂，从而在半导体衬底中形成第二掺杂区，并且还限定半导体衬底内的渐变结。