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11.发明申请公开(公告)号：US20100141324A1
公开(公告)日：2010-06-10
申请号：US12330768
申请日：2008-12-09
申请人： Chua-Chin Wang , Tzung-Je Lee , Yi-Cheng Liu , Kuo-Chan Huang
发明人： Chua-Chin Wang , Tzung-Je Lee , Yi-Cheng Liu , Kuo-Chan Huang
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： An output buffer circuit includes a high voltage detecting circuit, a dynamic gate bias generating circuit, an output stage circuit and a pad voltage detector. The high voltage detecting circuit detects a power supply voltage and generates a first and a second determining signals and a first and a second bias voltages according to the power supply voltage. The dynamic gate bias generating circuit is biased by the first and the second bias voltages and receives the first and the second determining signals, for converting logic control signals into corresponding gate bias voltages according to the first and the second determining signals. The pad voltage detector detects a voltage of an I/O pad and provides a pad voltage detecting signal for the output stage circuit to modify an output signal outputted to an I/O pad. A mixed-voltage input/output (I/O) buffer is disclosed herein.
摘要翻译： 输出缓冲电路包括高电压检测电路，动态栅极偏置产生电路，输出级电路和焊盘电压检测器。 高电压检测电路检测电源电压，并根据电源电压产生第一和第二确定信号以及第一和第二偏置电压。 动态栅极偏置产生电路被第一和第二偏置电压偏置，并接收第一和第二确定信号，用于根据第一和第二确定信号将逻辑控制信号转换成相应的栅极偏置电压。 焊盘电压检测器检测I / O焊盘的电压，并为输出级电路提供焊盘电压检测信号，以修改输出到I / O焊盘的输出信号。 本文公开了混合电压输入/输出（I / O）缓冲器。
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公开(公告)号：US08165258B2
公开(公告)日：2012-04-24
申请号：US12189204
申请日：2008-08-11
申请人： Meng-Chih Weng , Kuo-Chan Huang
发明人： Meng-Chih Weng , Kuo-Chan Huang
IPC分类号： H03D3/24
摘要： A clock generating device includes: a frequency divider having an input node coupled to a transmission interface for generating a reference clock signal according to an input data received from the transmission interface; and a clock/data recovery circuit having a data input node coupled to the transmission interface and a reference clock input node coupled to an output node of the frequency divider, for generating an output clock signal according to one of the input data received at the data input node and the reference clock signal received at the reference clock input node.
摘要翻译： 时钟产生装置包括：分频器，具有耦合到传输接口的输入节点，用于根据从传输接口接收的输入数据产生参考时钟信号; 以及具有耦合到所述传输接口的数据输入节点和耦合到所述分频器的输出节点的参考时钟输入节点的时钟/数据恢复电路，用于根据在所述数据处接收到的所述输入数据之一产生输出时钟信号 输入节点和参考时钟输入节点接收的参考时钟信号。
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公开(公告)号：US20080252783A1
公开(公告)日：2008-10-16
申请号：US11896216
申请日：2007-08-30
申请人： Tsung-Yi Su , Kuo-Chan Huang
发明人： Tsung-Yi Su , Kuo-Chan Huang
IPC分类号： H04N5/08
摘要： In a device for separating a synchronous signal in a video signal, a capacitor receives the video signal to obtain a coupling signal, a level determining circuit receives the coupling signal and compares a voltage level of the coupling signal with a number of reference voltages. The reference voltages define several reference voltage ranges, one of which is a predetermined reference voltage range. The level determining circuit outputs an adjusting signal according to a reference voltage range corresponding to a minimum voltage level of the coupling signal within a predetermined time period. A level adjusting circuit has several current sources for receiving the adjusting signal and thus controls the current sources to adjust a DC level of the coupling signal. A synchronous signal separating circuit separates the synchronous signal from the coupling signal when the minimum voltage level of the coupling signal is substantially within the predetermined reference voltage range.
摘要翻译： 在用于分离视频信号中的同步信号的装置中，电容器接收视频信号以获得耦合信号，电平确定电路接收耦合信号并将耦合信号的电压电平与多个参考电压进行比较。 参考电压定义了几个参考电压范围，其中一个参考电压范围是预定的参考电压范围。 电平确定电路根据与预定时间段内的耦合信号的最小电压电平相对应的参考电压范围输出调整信号。 电平调整电路具有几个用于接收调节信号的电流源，从而控制电流源来调节耦合信号的直流电平。 当耦合信号的最小电压电平基本上在预定参考电压范围内时，同步信号分离电路将同步信号与耦合信号分离。
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14.发明授权公开(公告)号：US06501449B1
公开(公告)日：2002-12-31
申请号：US09457234
申请日：1999-12-08
申请人： Kuo-Chan Huang
发明人： Kuo-Chan Huang
IPC分类号： G09G500
CPC分类号： G09G3/3283 , G09G3/3216 , G09G3/3241 , G09G2310/0251 , G09G2320/0233
摘要： The present invention generally relates to a high matching precision organic light emitting diode (OLED) driver by using a current-cascaded method, and more particularly, to a method in which the current-cascaded method is used so as to reduce the driving current mismatching brought about by the drifting in the parameters during different fabrication procedures, and thus improve the display quality. Among the plurality of driving integrated circuits (IC's), the internal circuit of each IC comprises a first operational amplifier, the output of which is connected to a plurality of output transistors that are further connected to a current mirror. The outputs of said plurality of output transistors are connected to other plurality of driving IC's respectively so as to achieve output current matching between other driving IC's.
摘要翻译： 本发明一般涉及通过使用电流级联方法的高匹配精度的有机发光二极管（OLED）驱动器，更具体地，涉及使用电流级联方法以减少驱动电流不匹配的方法 在不同的制造过程中由参数漂移引起的，从而提高显示质量。 在多个驱动集成电路（IC）中，每个IC的内部电路包括第一运算放大器，其输出端连接到进一步连接到电流镜的多个输出晶体管。 所述多个输出晶体管的输出分别连接到其它多个驱动IC，以实现其它驱动IC之间的输出电流匹配。
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15.发明授权Source driver output stage circuit, buffer circuit and voltage adjusting method thereof 有权源极驱动器输出级电路，缓冲电路及其电压调整方法公开(公告)号：US09413310B2
公开(公告)日：2016-08-09
申请号：US11594774
申请日：2006-11-09
申请人： Kuo-Chan Huang , Chih-Haur Huang
发明人： Kuo-Chan Huang , Chih-Haur Huang
IPC分类号： H03F3/217
CPC分类号： H03F3/217 , G09G2310/0275 , G09G2320/0252 , G09G2330/021 , G09G2330/028 , H03F2200/78
摘要： A buffer circuit applied to a source driver output stage circuit includes a buffer and a D-class amplifier. The buffer is coupled to an input voltage for accordingly outputting an output voltage. The D-class amplifier includes a comparator and a switch device. The comparator is for comparing the input voltage and the output voltage and accordingly outputting a comparison signal. The switch device is coupled to an operational voltage for adjusting the output voltage according to the comparison signal.
摘要翻译： 应用于源极驱动器输出级电路的缓冲电路包括缓冲器和D级放大器。 缓冲器耦合到输入电压，从而相应地输出输出电压。 D级放大器包括比较器和开关装置。 比较器用于比较输入电压和输出电压，从而输出比较信号。 开关装置耦合到用于根据比较信号调节输出电压的工作电压。
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公开(公告)号：US20110284984A1
公开(公告)日：2011-11-24
申请号：US12781825
申请日：2010-05-18
IPC分类号： H01L31/0224 , H01L31/18
CPC分类号： H01L27/14636 , H01L27/1464 , H01L27/1469 , H01L2224/48091 , H01L2924/00014
摘要： The present invention provides an image sensor and a fabricating method thereof capable of approaching higher quantum efficiency and reducing cost. The method comprises: providing a substrate; forming a pixel region on a top surface of the substrate; forming an interlayer insulating layer and at least a metal line on the pixel region; forming an isolation carrier layer having a hole array therein on the interlayer insulating layer; grinding a lower surface of the substrate to reduce the thickness of the substrate; placing a plurality of conductors into the hole array to form a plurality of bumps on the isolation carrier layer.
摘要翻译： 本发明提供能够接近更高量子效率并降低成本的图像传感器及其制造方法。 该方法包括：提供衬底; 在所述基板的顶表面上形成像素区域; 在所述像素区域上形成层间绝缘层和至少金属线; 在层间绝缘层上形成具有孔阵列的隔离载体层; 研磨衬底的下表面以减小衬底的厚度; 将多个导体放置到孔阵列中以在隔离载体层上形成多个凸起。
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17.发明授权公开(公告)号：US07863936B1
公开(公告)日：2011-01-04
申请号：US12785505
申请日：2010-05-24
申请人： Chih-Min Liu , Ping-Hung Yin , Kuo-Chan Huang
发明人： Chih-Min Liu , Ping-Hung Yin , Kuo-Chan Huang
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： H03K19/018564 , H03K19/018585
摘要： A driving circuit includes at least a driving unit, a first processing unit and a second processing unit. The driving circuit includes a first bias component, a second bias component, a first pre-emphasis unit, a second pre-emphasis unit, and a transmitter unit. The first bias component has a first node coupled to a first reference voltage and a second node for outputting a first bias current. The second bias component has a first node for draining a second bias current and a second node coupled to a second reference voltage different from the first reference voltage.
摘要翻译： 驱动电路至少包括驱动单元，第一处理单元和第二处理单元。 驱动电路包括第一偏置分量，第二偏压分量，第一预加重单元，第二预加重单元和发送器单元。 第一偏置分量具有耦合到第一参考电压的第一节点和用于输出第一偏置电流的第二节点。 第二偏置组件具有用于排出第二偏置电流的第一节点和耦合到不同于第一参考电压的第二参考电压的第二节点。
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公开(公告)号：US20100085089A1
公开(公告)日：2010-04-08
申请号：US12246465
申请日：2008-10-06
申请人： Meng-Chih Weng , Kuo-Chan Huang
发明人： Meng-Chih Weng , Kuo-Chan Huang
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03L7/091 , H03L7/0995 , H03L7/18
摘要： A phase-locked loop circuit for generating an output signal includes a phase frequency detector (PFD), a processing module, and a clock generator. The PFD is implemented for generating a plurality of indicating signals according to a first reference signal and a feedback signal, where the feedback signal is generated according to the output signal. The processing module is coupled to the PFD, and is implemented for generating a control signal according to the indicating signals and a plurality of clock signals, where the clock signals have an identical frequency but different phases. The clock generator is coupled to the processing module, and is implemented for generating the clock signals according to the control signal. The output signal is generated according to a specific clock signal selected from the clock signals.
摘要翻译： 用于产生输出信号的锁相环电路包括相位频率检测器（PFD），处理模块和时钟发生器。 PFD被实现为根据第一参考信号和反馈信号产生多个指示信号，其中根据输出信号产生反馈信号。 处理模块耦合到PFD，并被实现用于根据指示信号和多个时钟信号产生控制信号，其中时钟信号具有相同的频率但不同的相位。 时钟发生器耦合到处理模块，并被实现为根据控制信号产生时钟信号。 根据从时钟信号中选择的特定时钟信号产生输出信号。
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公开(公告)号：US20100034330A1
公开(公告)日：2010-02-11
申请号：US12189204
申请日：2008-08-11
申请人： Meng-Chih Weng , Kuo-Chan Huang
发明人： Meng-Chih Weng , Kuo-Chan Huang
IPC分类号： H04L7/00
摘要： A clock generating device includes: a frequency divider having an input node coupled to a transmission interface for generating a reference clock signal according to an input data received from the transmission interface; and a clock/data recovery circuit having a data input node coupled to the transmission interface and a reference clock input node coupled to an output node of the frequency divider, for generating an output clock signal according to one of the input data received at the data input node and the reference clock signal received at the reference clock input node.
摘要翻译： 时钟产生装置包括：分频器，具有耦合到传输接口的输入节点，用于根据从传输接口接收的输入数据产生参考时钟信号; 以及具有耦合到所述传输接口的数据输入节点和耦合到所述分频器的输出节点的参考时钟输入节点的时钟/数据恢复电路，用于根据在所述数据处接收到的所述输入数据之一产生输出时钟信号 输入节点和参考时钟输入节点接收的参考时钟信号。
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公开(公告)号：US20090112499A1
公开(公告)日：2009-04-30
申请号：US12117176
申请日：2008-05-08
IPC分类号： G01R29/26
CPC分类号： G01R31/31709
摘要： The device for jitter measurement and a method thereof are provided. The device for jitter measure includes a signal retrieving module, a signal amplifying module, an edge detecting module, and a time-to-digital converting module. The signal retrieving module receives a signal-under-test, and retrieves a first pulse signal having a pulse width equal to a period of the signal-under-test. The signal amplifying module amplifies the pulse width of the first pulse signal and thereby generates a second pulse signal. The edge detecting module detects a rising edge and a falling edge of the second pulse signal, and generates a first indication signal and a second indication signal according to the respective detected results. The time-to-digital converting module converts the pulse width of the second pulse signal existed in time domain to a digital signal according to the first indication signal and the second indication signal.
摘要翻译： 提供抖动测量装置及其方法。 用于抖动测量的装置包括信号检索模块，信号放大模块，边缘检测模块和时间 - 数字转换模块。 信号检索模块接收待测信号，并检索具有等于被测信号的周期的脉冲宽度的第一脉冲信号。 信号放大模块放大第一脉冲信号的脉冲宽度，从而产生第二脉冲信号。 边缘检测模块检测第二脉冲信号的上升沿和下降沿，并根据各个检测结果生成第一指示信号和第二指示信号。 时间 - 数字转换模块根据第一指示信号和第二指示信号将时域中存在的第二脉冲信号的脉冲宽度转换为数字信号。
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