公开(公告)号：US08165258B2

公开(公告)日：2012-04-24

申请号：US12189204

申请日：2008-08-11

申请人： Meng-Chih Weng ,  Kuo-Chan Huang

发明人： Meng-Chih Weng ,  Kuo-Chan Huang

IPC分类号： H03D3/24

CPC分类号： H04L7/033 ,  H03L7/087 ,  H03L7/095 ,  H03L7/113 ,  H03L7/18 ,  H04L7/046 ,  H04L7/10

摘要： A clock generating device includes: a frequency divider having an input node coupled to a transmission interface for generating a reference clock signal according to an input data received from the transmission interface; and a clock/data recovery circuit having a data input node coupled to the transmission interface and a reference clock input node coupled to an output node of the frequency divider, for generating an output clock signal according to one of the input data received at the data input node and the reference clock signal received at the reference clock input node.

摘要翻译： 时钟产生装置包括：分频器，具有耦合到传输接口的输入节点，用于根据从传输接口接收的输入数据产生参考时钟信号; 以及具有耦合到所述传输接口的数据输入节点和耦合到所述分频器的输出节点的参考时钟输入节点的时钟/数据恢复电路，用于根据在所述数据处接收到的所述输入数据之一产生输出时钟信号 输入节点和参考时钟输入节点接收的参考时钟信号。

公开(公告)号：US20100085089A1

公开(公告)日：2010-04-08

申请号：US12246465

申请日：2008-10-06

申请人： Meng-Chih Weng ,  Kuo-Chan Huang

发明人： Meng-Chih Weng ,  Kuo-Chan Huang

IPC分类号： H03L7/06

CPC分类号： H03L7/089 ,  H03L7/091 ,  H03L7/0995 ,  H03L7/18

摘要： A phase-locked loop circuit for generating an output signal includes a phase frequency detector (PFD), a processing module, and a clock generator. The PFD is implemented for generating a plurality of indicating signals according to a first reference signal and a feedback signal, where the feedback signal is generated according to the output signal. The processing module is coupled to the PFD, and is implemented for generating a control signal according to the indicating signals and a plurality of clock signals, where the clock signals have an identical frequency but different phases. The clock generator is coupled to the processing module, and is implemented for generating the clock signals according to the control signal. The output signal is generated according to a specific clock signal selected from the clock signals.

摘要翻译： 用于产生输出信号的锁相环电路包括相位频率检测器（PFD），处理模块和时钟发生器。 PFD被实现为根据第一参考信号和反馈信号产生多个指示信号，其中根据输出信号产生反馈信号。 处理模块耦合到PFD，并被实现用于根据指示信号和多个时钟信号产生控制信号，其中时钟信号具有相同的频率但不同的相位。 时钟发生器耦合到处理模块，并被实现为根据控制信号产生时钟信号。 根据从时钟信号中选择的特定时钟信号产生输出信号。

公开(公告)号：US20100034330A1

公开(公告)日：2010-02-11

申请号：US12189204

申请日：2008-08-11

申请人： Meng-Chih Weng ,  Kuo-Chan Huang

发明人： Meng-Chih Weng ,  Kuo-Chan Huang

IPC分类号： H04L7/00

CPC分类号： H04L7/033 ,  H03L7/087 ,  H03L7/095 ,  H03L7/113 ,  H03L7/18 ,  H04L7/046 ,  H04L7/10

摘要： A clock generating device includes: a frequency divider having an input node coupled to a transmission interface for generating a reference clock signal according to an input data received from the transmission interface; and a clock/data recovery circuit having a data input node coupled to the transmission interface and a reference clock input node coupled to an output node of the frequency divider, for generating an output clock signal according to one of the input data received at the data input node and the reference clock signal received at the reference clock input node.

摘要翻译： 时钟产生装置包括：分频器，具有耦合到传输接口的输入节点，用于根据从传输接口接收的输入数据产生参考时钟信号; 以及具有耦合到所述传输接口的数据输入节点和耦合到所述分频器的输出节点的参考时钟输入节点的时钟/数据恢复电路，用于根据在所述数据处接收到的所述输入数据之一产生输出时钟信号 输入节点和参考时钟输入节点接收的参考时钟信号。

公开(公告)号：US07786773B2

公开(公告)日：2010-08-31

申请号：US12246465

申请日：2008-10-06

申请人： Meng-Chih Weng ,  Kuo-Chan Huang

发明人： Meng-Chih Weng ,  Kuo-Chan Huang

IPC分类号： H03L7/06

CPC分类号： H03L7/089 ,  H03L7/091 ,  H03L7/0995 ,  H03L7/18

摘要： A phase-locked loop circuit for generating an output signal includes a phase frequency detector (PFD), a processing module, and a clock generator. The PFD is implemented for generating a plurality of indicating signals according to a first reference signal and a feedback signal, where the feedback signal is generated according to the output signal. The processing module is coupled to the PFD, and is implemented for generating a control signal according to the indicating signals and a plurality of clock signals, where the clock signals have an identical frequency but different phases. The clock generator is coupled to the processing module, and is implemented for generating the clock signals according to the control signal. The output signal is generated according to a specific clock signal selected from the clock signals.

摘要翻译： 用于产生输出信号的锁相环电路包括相位频率检测器（PFD），处理模块和时钟发生器。 PFD被实现为根据第一参考信号和反馈信号产生多个指示信号，其中根据输出信号产生反馈信号。 处理模块耦合到PFD，并被实现用于根据指示信号和多个时钟信号产生控制信号，其中时钟信号具有相同的频率但不同的相位。 时钟发生器耦合到处理模块，并被实现为根据控制信号产生时钟信号。 根据从时钟信号中选择的特定时钟信号产生输出信号。

公开(公告)号：US08212590B2

公开(公告)日：2012-07-03

申请号：US13067598

申请日：2011-06-13

申请人： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

发明人： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

IPC分类号： H03B1/00

CPC分类号： H03K19/0013 ,  H03K3/356113 ,  H03K19/018521

摘要： A mixed-voltage I/O buffer includes an input buffer circuit. The input buffer circuit includes a first inverter, a first voltage level limiting circuit, a first voltage level pull-up circuit, an input stage circuit, and a logic calibration circuit. The first inverter inverts an input signal to generate a first control signal. The first voltage level limiting circuit limits voltage level of an external signal to generate the input signal transmitted to the first inverter to prevent electrical overstress of the first inverter. The first voltage level pull-up circuit is controlled by the first control signal to pull up voltage level of the input signal inputted into the first inverter. The input stage circuit receives the first control signal to generate corresponding digital signals inputted into a core circuit. The logic calibration circuit calibrates voltage level of the first control signal when the first inverter mis-operates due to the input signal having a low voltage level.

摘要翻译： 混合电压I / O缓冲器包括输入缓冲电路。 输入缓冲电路包括第一反相器，第一电压电平限制电路，第一电压电平上拉电路，输入级电路和逻辑校准电路。 第一反相器反相输入信号以产生第一控制信号。 第一电压电平限制电路限制外部信号的电压电平，以产生传输到第一逆变器的输入信号，以防止第一逆变器的电过载。 第一电压上拉电路由第一控制信号控制，以提高输入到第一反相器的输入信号的电压电平。 输入级电路接收第一控制信号以产生输入到核心电路的相应的数字信号。 当由于输入信号具有低电压电平而使第一反相器误操作时，逻辑校准电路校准第一控制信号的电压电平。

公开(公告)号：US20100277216A1

公开(公告)日：2010-11-04

申请号：US12835202

申请日：2010-07-13

申请人： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang ,  Tie-Yan Chang

发明人： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang ,  Tie-Yan Chang

IPC分类号： H03L5/00

CPC分类号： H03K19/018521 ,  H03K19/018528

摘要： An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit (10) and operates in a transmitting mode according to the control signal. The output buffer circuit converts the data signal into an output signal at a first voltage level or a ground voltage level according to the data signal logic level and a supply voltage (VDDIO). The supply voltage is adjusted to pull up or pull down the first voltage level of the output signal.

摘要翻译： 提供输出缓冲电路。 输出缓冲电路从第一核心电路（10）接收控制信号（OE）和数据信号（Dout），并根据控制信号在发送模式下工作。 输出缓冲电路根据数据信号逻辑电平和电源电压（VDDIO）将数据信号转换成第一电压电平或接地电压电平的输出信号。 电源电压被调整为上拉或下拉输出信号的第一电压电平。

公开(公告)号：US07786760B2

公开(公告)日：2010-08-31

申请号：US12193299

申请日：2008-08-18

申请人： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang ,  Tie-Yan Chang

发明人： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang ,  Tie-Yan Chang

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521 ,  H03K19/018528

摘要： An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit (10) and operates in a transmitting mode according to the control signal. The output buffer circuit converts the data signal into an output signal at a first voltage level or a ground voltage level according to the data signal logic level and a supply voltage (VDDIO). The supply voltage is adjusted to pull up or pull down the first voltage level of the output signal.

摘要翻译： 提供输出缓冲电路。 输出缓冲电路从第一核心电路（10）接收控制信号（OE）和数据信号（Dout），并根据控制信号在发送模式下工作。 输出缓冲电路根据数据信号逻辑电平和电源电压（VDDIO）将数据信号转换成第一电压电平或接地电压电平的输出信号。 电源电压被调整为上拉或下拉输出信号的第一电压电平。

公开(公告)号：US20080252783A1

公开(公告)日：2008-10-16

申请号：US11896216

申请日：2007-08-30

申请人： Tsung-Yi Su ,  Kuo-Chan Huang

发明人： Tsung-Yi Su ,  Kuo-Chan Huang

IPC分类号： H04N5/08

CPC分类号： H04N5/18 ,  H04N5/08

摘要： In a device for separating a synchronous signal in a video signal, a capacitor receives the video signal to obtain a coupling signal, a level determining circuit receives the coupling signal and compares a voltage level of the coupling signal with a number of reference voltages. The reference voltages define several reference voltage ranges, one of which is a predetermined reference voltage range. The level determining circuit outputs an adjusting signal according to a reference voltage range corresponding to a minimum voltage level of the coupling signal within a predetermined time period. A level adjusting circuit has several current sources for receiving the adjusting signal and thus controls the current sources to adjust a DC level of the coupling signal. A synchronous signal separating circuit separates the synchronous signal from the coupling signal when the minimum voltage level of the coupling signal is substantially within the predetermined reference voltage range.

摘要翻译： 在用于分离视频信号中的同步信号的装置中，电容器接收视频信号以获得耦合信号，电平确定电路接收耦合信号并将耦合信号的电压电平与多个参考电压进行比较。 参考电压定义了几个参考电压范围，其中一个参考电压范围是预定的参考电压范围。 电平确定电路根据与预定时间段内的耦合信号的最小电压电平相对应的参考电压范围输出调整信号。 电平调整电路具有几个用于接收调节信号的电流源，从而控制电流源来调节耦合信号的直流电平。 当耦合信号的最小电压电平基本上在预定参考电压范围内时，同步信号分离电路将同步信号与耦合信号分离。

公开(公告)号：US06501449B1

公开(公告)日：2002-12-31

申请号：US09457234

申请日：1999-12-08

申请人： Kuo-Chan Huang

发明人： Kuo-Chan Huang

IPC分类号： G09G500

CPC分类号： G09G3/3283 ,  G09G3/3216 ,  G09G3/3241 ,  G09G2310/0251 ,  G09G2320/0233

摘要： The present invention generally relates to a high matching precision organic light emitting diode (OLED) driver by using a current-cascaded method, and more particularly, to a method in which the current-cascaded method is used so as to reduce the driving current mismatching brought about by the drifting in the parameters during different fabrication procedures, and thus improve the display quality. Among the plurality of driving integrated circuits (IC's), the internal circuit of each IC comprises a first operational amplifier, the output of which is connected to a plurality of output transistors that are further connected to a current mirror. The outputs of said plurality of output transistors are connected to other plurality of driving IC's respectively so as to achieve output current matching between other driving IC's.

摘要翻译： 本发明一般涉及通过使用电流级联方法的高匹配精度的有机发光二极管（OLED）驱动器，更具体地，涉及使用电流级联方法以减少驱动电流不匹配的方法 在不同的制造过程中由参数漂移引起的，从而提高显示质量。 在多个驱动集成电路（IC）中，每个IC的内部电路包括第一运算放大器，其输出端连接到进一步连接到电流镜的多个输出晶体管。 所述多个输出晶体管的输出分别连接到其它多个驱动IC，以实现其它驱动IC之间的输出电流匹配。

公开(公告)号：US09413310B2

公开(公告)日：2016-08-09

申请号：US11594774

申请日：2006-11-09

申请人： Kuo-Chan Huang ,  Chih-Haur Huang

发明人： Kuo-Chan Huang ,  Chih-Haur Huang

IPC分类号： H03F3/217

CPC分类号： H03F3/217 ,  G09G2310/0275 ,  G09G2320/0252 ,  G09G2330/021 ,  G09G2330/028 ,  H03F2200/78

摘要： A buffer circuit applied to a source driver output stage circuit includes a buffer and a D-class amplifier. The buffer is coupled to an input voltage for accordingly outputting an output voltage. The D-class amplifier includes a comparator and a switch device. The comparator is for comparing the input voltage and the output voltage and accordingly outputting a comparison signal. The switch device is coupled to an operational voltage for adjusting the output voltage according to the comparison signal.

摘要翻译： 应用于源极驱动器输出级电路的缓冲电路包括缓冲器和D级放大器。 缓冲器耦合到输入电压，从而相应地输出输出电压。 D级放大器包括比较器和开关装置。 比较器用于比较输入电压和输出电压，从而输出比较信号。 开关装置耦合到用于根据比较信号调节输出电压的工作电压。