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公开(公告)号：US20090170262A1
公开(公告)日：2009-07-02
申请号：US12397905
申请日：2009-03-04
IPC分类号： H01L21/8239
CPC分类号： H01L27/115 , H01L27/11521 , Y10S438/926 , Y10S438/962
摘要： A virtual ground memory array (VGA) is formed by a storage layer over a substrate with a conductive layer over the storage layer. The conductive layer is opened according to a patterned photoresist layer. The openings are implanted to form source/drain lines in the substrate, then filled with a layer of dielectric material. Chemical mechanical polishing (CMP) is then performed until the top of the conductive layer is exposed. This leaves dielectric spacers over the source/drain lines and conductive material between the dielectric spacers. Word lines are then formed over the conductive material and the dielectric spacers. As an alternative, instead of using a conductive layer, a sacrificial layer is used that is removed after the CMP step. After removing the sacrificial portions, the word lines are formed. In both cases, dielectric spacers reduce gate/drain capacitance and the distance from substrate to gate is held constant across the channel.
摘要翻译： 虚拟接地存储器阵列（VGA）由存储层上的存储层形成在衬底上，在存储层上方具有导电层。 根据图案化的光致抗蚀剂层打开导电层。 注入开口以在衬底中形成源极/漏极线，然后填充一层电介质材料。 然后进行化学机械抛光（CMP），直到暴露导电层的顶部。 这使得源极/漏极线之间的电介质间隔物和电介质间隔物之间的导电材料留下。 然后在导电材料和电介质间隔物上形成字线。 作为替代，代替使用导电层，使用在CMP步骤之后去除的牺牲层。 在去除牺牲部分之后，形成字线。 在这两种情况下，介质间隔物减少了栅极/漏极电容，并且从衬底到栅极的距离在通道上保持恒定。
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12.发明授权公开(公告)号：US07285819B2
公开(公告)日：2007-10-23
申请号：US11188582
申请日：2005-07-25
IPC分类号： H01L29/788
CPC分类号： H01L29/7887 , B82Y10/00 , H01L21/28273 , H01L27/115 , H01L29/4232 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H01L29/7923
摘要： An array of storage cells include a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes a layer of discontinuous storage elements (DSEs). A control gate overlies the first trench. The control gate may run perpendicular to the trenches and traverse the first and second trenches. In another implementation, the control gate runs parallel with the trenches. The storage cell may include one or more diffusion regions occupying an upper surface of the substrate between the first and second trenches. The diffusion region may reside between first and second control gates that are parallel to the trenches. Alternatively, a pair of diffusion regions may occur on either side of a control gate that is perpendicular to the trenches.
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公开(公告)号：US20070020820A1
公开(公告)日：2007-01-25
申请号：US11188909
申请日：2005-07-25
IPC分类号： H01L21/8232
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0475 , H01L27/11519 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/7885 , Y10S977/707 , Y10S977/712
摘要： A process for forming an electronic device can include forming a first set of discontinuous storage elements over a primary surface of a substrate and forming a trench within the substrate. The process can also include forming a second set of discontinuous storage elements within the trench. The process can further include forming a first gate electrode within the trench, wherein a discontinuous storage element lies between the first gate electrode and a wall of the trench. The process can still further include removing a part of the second set of discontinuous storage elements and forming a second gate electrode over the first gate electrode. After forming the second gate electrode, substantially none of the second set of discontinuous storage elements lies along the wall of the trench at an elevation between an upper surface of the first gate electrode and the primary surface of the substrate.
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公开(公告)号：US20070018240A1
公开(公告)日：2007-01-25
申请号：US11188910
申请日：2005-07-25
IPC分类号： H01L29/94
CPC分类号： H01L29/7887 , B82Y10/00 , G11C16/0475 , H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/66825 , Y10S977/707 , Y10S977/712
摘要： An electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a first set of discontinuous storage elements that overlie a primary surface of the substrate and a second set of discontinuous storage elements that lie within the trench. The electronic device can also include a first gate electrode, wherein substantially none of the discontinuous storage elements lies along the wall of the trench at an elevation between and upper surface of the first gate electrode and the primary surface of the substrate. The electronic device can also include a second gate electrode overlying the first gate electrode and the primary surface. In another embodiment, a conductive line can be electrically connected to one or more rows or columns of memory cells, and another conductive line can be more rows or more columns of memory cells.
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公开(公告)号：US07391659B2
公开(公告)日：2008-06-24
申请号：US11341809
申请日：2006-01-27
IPC分类号： G11C29/00
CPC分类号： G11C16/0466 , G11C16/12 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A memory cell is programmed by injecting charge into a charge storage layer of the memory cell. A desired programmed charge results in the charge storage layer over an edge portion of a channel region of the memory cell. An undesired programmed charge results in the charge storage layer over an inner portion of the channel region. Charge tunneling is used to substantially remove the undesired programmed charge in the charge storage layer. In one form the memory cell has a substrate having a channel region, a first dielectric layer over the substrate and a charge storage layer over the first dielectric layer. A second dielectric layer over the charge storage layer has a first portion that is thicker than a second portion to selectively control the charge tunneling.
摘要翻译： 通过将电荷注入存储器单元的电荷存储层来编程存储器单元。 期望的编程电荷导致电荷存储层超过存储器单元的沟道区域的边缘部分。 不期望的编程电荷导致电荷存储层在通道区域的内部部分上。 电荷隧道用于基本上去除电荷存储层中的不期望的编程电荷。 在一种形式中，存储单元具有衬底，其具有沟道区，衬底上的第一介电层和位于第一介电层上的电荷存储层。 电荷存储层上的第二电介质层具有比第二部分厚的第一部分，以选择性地控制电荷隧穿。
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公开(公告)号：US07317222B2
公开(公告)日：2008-01-08
申请号：US11341813
申请日：2006-01-27
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/4234 , H01L29/66833
摘要： A memory cell is programmed by injecting charge into a charge storage layer of the memory cell. A desired programmed charge results in the charge storage layer over an edge portion of a channel region of the memory cell. An undesired programmed charge results in the charge storage layer over an inner portion of the channel region. Charge tunneling is used to substantially remove the undesired programmed charge in the charge storage layer. In one form the memory cell has a substrate having a channel region, a first dielectric layer over the substrate and a charge storage layer over the first dielectric layer. A second dielectric layer over the charge storage layer has a first portion that is thicker than a second portion to selectively control the charge tunneling.
摘要翻译： 通过将电荷注入存储器单元的电荷存储层来编程存储器单元。 期望的编程电荷导致电荷存储层超过存储器单元的沟道区域的边缘部分。 不期望的编程电荷导致电荷存储层在通道区域的内部部分上。 电荷隧道用于基本上去除电荷存储层中的不期望的编程电荷。 在一种形式中，存储单元具有衬底，其具有沟道区，衬底上的第一介电层和位于第一介电层上的电荷存储层。 电荷存储层上的第二电介质层具有比第二部分厚的第一部分，以选择性地控制电荷隧穿。
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公开(公告)号：US07105395B2
公开(公告)日：2006-09-12
申请号：US10930891
申请日：2004-08-31
IPC分类号： H01L29/72
CPC分类号： H01L29/0847 , H01L29/7881 , H01L29/7885
摘要： A non-volatile memory (NVM) has a silicon germanium (SiGe) drain that is progressively more heavily doped toward the surface of the substrate. The substrate is preferably silicon and the drain is formed by first forming a cavity in the substrate in the drain location. SiGe is epitaxially grown in the cavity with an increasing doping level. Thus, the PN junction between the substrate and the drain is lightly doped on both the P and N side. The drain progressively becomes more heavily doped until the maximum desired doping level is reached, and the remaining portion of the SiGe drain is doped at this maximum desired level. As a further enhancement, the perimeter of the SiGe in the substrate is the same conductivity type as that of the substrate and channel. Thus a portion of the channel is in the SiGe.
摘要翻译： 非易失性存储器（NVM）具有朝向衬底表面逐渐更加掺杂的硅锗（SiGe）漏极。 衬底优选为硅，并且通过首先在漏极位置中的衬底中形成空腔来形成漏极。 SiGe在掺杂水平增加的情况下外延生长。 因此，衬底和漏极之间的PN结在P和N侧都被轻掺杂。 漏极逐渐变得更加重掺杂，直到达到最大期望的掺杂水平，并且SiGe漏极的剩余部分以该最大期望水平掺杂。 作为进一步的增强，衬底中SiGe的周长与衬底和沟道的导电类型相同。 因此，通道的一部分在SiGe中。
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18.发明授权Process for forming an electronic device including discontinuous storage elements 失效用于形成包括不连续存储元件的电子设备的方法公开(公告)号：US07619275B2
公开(公告)日：2009-11-17
申请号：US11188935
申请日：2005-07-25
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0475 , H01L21/7624 , H01L27/11519 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336
摘要： A process for forming an electronic device can include forming a trench within a substrate, wherein the trench includes a wall and a bottom. The process can also include including forming a portion of discontinuous storage elements that lie within the trench, and forming a first gate electrode within the trench after forming the discontinuous storage elements. At least one discontinuous storage element lies along the wall of the trench at an elevation between an upper surface of the first gate electrode and a primary surface of the substrate. The process can also include forming a second gate electrode overlying the first gate electrode and the primary surface of the substrate.
摘要翻译： 用于形成电子器件的方法可以包括在衬底内形成沟槽，其中沟槽包括壁和底部。 该方法还可以包括形成位于沟槽内的不连续存储元件的一部分，以及在形成不连续存储元件之后在沟槽内形成第一栅电极。 至少一个不连续的存储元件位于第一栅电极的上表面和衬底的主表面之间的海拔处的沟槽的壁处。 该工艺还可以包括形成覆盖在第一栅电极和衬底的主表面上的第二栅电极。
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公开(公告)号：US07544980B2
公开(公告)日：2009-06-09
申请号：US11342155
申请日：2006-01-27
IPC分类号： H01L29/06
CPC分类号： H01L29/7881 , B82Y10/00 , G11C16/0466 , G11C2216/06 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/42348 , H01L29/66825 , H01L29/785 , H01L29/792
摘要： A memory cell is implemented using a semiconductor fin in which the channel region is along a sidewall of the fin between source and drains regions. One portion of the channel region has a select gate adjacent to it and another other portion has the control gate adjacent to it with a charge storage structure there between. In some embodiments, independent control gate structures are located adjacent opposite sidewalls of the fin so as to implement two memory cells.
摘要翻译： 使用半导体鳍片实现存储器单元，其中沟道区域沿着源极和漏极区域之间的鳍片的侧壁。 通道区域的一部分具有与其相邻的选择栅极，而另一部分具有与其相邻的控制栅极，其间具有电荷存储结构。 在一些实施例中，独立的控制栅极结构位于鳍的相对侧壁附近，以便实现两个存储单元。
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公开(公告)号：US07195983B2
公开(公告)日：2007-03-27
申请号：US10930892
申请日：2004-08-31
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , H01L29/1608 , H01L29/267 , H01L29/66833 , H01L29/7881
摘要： A non-volatile memory (NVM) has a silicon germanium (SiGe) drain and a silicon carbon (SiC) source. The source being SiC provides for a stress on the channel that improves N channel mobility. The SiC also has a larger bandgap than the substrate, which is silicon. This results in it being more difficult to generate electron/hole pairs by impact ionization. Thus, it can be advantageous to use the SiC region for the drain during a read. The SiGe is used as the drain for programming and erase. The SiGe, having a smaller bandgap than the silicon substrate results in improved programming by generating electron/hole pairs by impact ionization and improved erasing by generating electron hole/pairs by band-to-band tunneling, both at lower voltage levels.
摘要翻译： 非易失性存储器（NVM）具有硅锗（SiGe）漏极和硅碳（SiC）源。 作为SiC的源提供通道上的应力，其改善N沟道迁移率。 SiC也具有比衬底更大的带隙，这是硅。 这导致通过冲击电离产生电子/空穴对更困难。 因此，在读取期间使用SiC区域用于漏极是有利的。 SiGe用作编程和擦除的漏极。 具有比硅衬底更小的带隙的SiGe通过在较低电压电平下通过产生电子/空穴对的冲击电离和通过频带隧穿产生电子空穴/对来改善擦除来改善编程。
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