公开(公告)号：US20080162954A1

公开(公告)日：2008-07-03

申请号：US11649326

申请日：2006-12-31

申请人： Paul Lassa ,  Paul Paternoster ,  Po-Shen Lai ,  Yongliang Wang

发明人： Paul Lassa ,  Paul Paternoster ,  Po-Shen Lai ,  Yongliang Wang

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

摘要： A plurality of separately powered data interface circuits, a controller circuit, and power switch circuits that collectively enable a supply of power to only one of the data interface circuits and disable the supply of power to the other data interface circuits.

摘要翻译： 多个单独供电的数据接口电路，控制器电路和功率开关电路，其共同地仅向数据接口电路之一提供电力，并且禁止向其它数据接口电路供电。

公开(公告)号：US06216193B1

公开(公告)日：2001-04-10

申请号：US09146252

申请日：1998-09-03

申请人： Po-Shen Lai ,  Autumn Jane Niu ,  Jerry Chun-Jen Kuo ,  John M. Chiang

发明人： Po-Shen Lai ,  Autumn Jane Niu ,  Jerry Chun-Jen Kuo ,  John M. Chiang

IPC分类号： G06F1300

CPC分类号： G06F13/385

摘要： A network interface includes a multiplexer that selectively supplies either a stored address from an address holding register, or a reload address from a reload address holding register, to a random access buffer memory based on a done delay signal (DMA_DONE_DLY). The done delay signal is generated by an advance signal generator in response to detection of a target initiated termination request on the PCI bus during a DMA data transfer from the random access buffer memory to the target. if the PCI bus transfer is interrupted, the reload address is supplied to the random access buffer memory to enable data output holding registers to be reloaded with the data lost by the target during the interrupted DMA transfer. The array of data output holding registers are capable of recovering from the interrupted PCI bus transfer and output the data set which the target (e.g., the host system memory) expects to receive. The reload address is also supplied to the address register to resume normal addressing by address holding register.

摘要翻译： 网络接口包括多路复用器，其基于完成的延迟信号（DMA_DONE_DLY），将存储的地址从地址保持寄存器或重载地址从重载地址保持寄存器选择性地提供给随机存取缓冲存储器。 响应于在从随机存取缓冲存储器到目标的DMA数据传输期间在PCI总线上检测到目标发起的终止请求，由提前信号发生器产生完成的延迟信号。 如果PCI总线传输中断，则重新加载地址被提供给随机存取缓冲存储器，以使数据输出保持寄存器在DMA中断期间由目标丢失的数据重新加载。 数据输出保持寄存器阵列能够从中断的PCI总线传送恢复，并输出目标（例如，主机系统存储器）期望接收的数据集。 重载地址也提供给地址寄存器，以通过地址保持寄存器恢复正常寻址。

公开(公告)号：US6145016A

公开(公告)日：2000-11-07

申请号：US146251

申请日：1998-09-03

申请人： Po-Shen Lai ,  Autumn Jane Niu ,  Jerry Chun-Ken Kuo

发明人： Po-Shen Lai ,  Autumn Jane Niu ,  Jerry Chun-Ken Kuo

IPC分类号： G06F13/12 ,  H04L12/56 ,  G06F13/14

CPC分类号： H04L49/9063 ,  G06F13/128 ,  H04L49/90 ,  H04L49/901

摘要： A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memory between the read and write controllers. The synchronization circuit determines the presence of a stored frame in the random access memory by asynchronously comparing write counter and read counter values. The memory management unit also includes a descriptor management unit for controlling DMA transfers between the transmit and receive buffers and the system memory. The descriptor management obtains descriptor lists from system memory based on descriptor index data supplied by the host CPU and verified as valid by the descriptor management, and releases control of the descriptor lists by writing to status locations in system memory.

摘要翻译： 网络接口设备包括用作发送和接收缓冲器的随机存取存储器，用于在主计算机总线和分组交换网络之间传输和接收数据帧。 网络接口设备包括用于每个发送和接收缓冲器的读和写控制器，其中每个写控制器在与相应的读控制器分离的时钟域中操作。 存储器管理单元还包括同步电路，其控制仲裁以访问读取和写入控制器之间的随机存取存储器。 同步电路通过异步比较写计数器和读计数器值来确定随机存取存储器中存储的帧的存在。 存储器管理单元还包括用于控制发送和接收缓冲器与系统存储器之间的DMA传输的描述符管理单元。 描述符管理基于由主机CPU提供的描述符索引数据从系统存储器中获取描述符列表，并通过描述符管理验证为有效，并通过写入系统存储器中的状态位置来释放对描述符列表的控制。

公开(公告)号：US6061767A

公开(公告)日：2000-05-09

申请号：US993531

申请日：1997-12-18

申请人： Jerry Chun-Jen Kuo ,  Po-Shen Lai ,  Autumn Jane Niu

发明人： Jerry Chun-Jen Kuo ,  Po-Shen Lai ,  Autumn Jane Niu

IPC分类号： H04L12/56 ,  G06F12/00

CPC分类号： H04L49/9047 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9021

摘要： A network interface device having a random access memory for buffering data between a host bus interface and a media access controller includes a buffer controller configured for storing a data frame in combination with tracking and status information associated with the storage of the data frame. The memory controller is configured for writing receive frame data received from a media access controller into the random access memory. The tracking and status information is stored in memory locations contiguous with the data frame to enable a read controller operating in a separate clock domain to access the status information and the corresponding data frame as a single data unit. Moreover, the disclosed embodiment stores the status information at the beginning of the stored data unit, enabling a controller reading the buffer memory to immediately determine the status of the corresponding stored data frame.

摘要翻译： 具有用于在主机总线接口和媒体访问控制器之间缓存数据的随机存取存储器的网络接口设备包括：缓冲器控制器，被配置为与跟踪数据帧和与数据帧的存储相关联的状态信息结合存储数据帧。 存储器控制器被配置为将从媒体访问控制器接收的接收帧数据写入随机存取存储器。 跟踪和状态信息存储在与数据帧相邻的存储器位置中，以使得在单独的时钟域中操作的读取控制器可以将状态信息和相应的数据帧作为单个数据单元访问。 此外，所公开的实施例将状态信息存储在所存储的数据单元的开始处，使得读取缓冲存储器的控制器能够立即确定对应的存储数据帧的状态。

公开(公告)号：US08347251B2

公开(公告)日：2013-01-01

申请号：US11967880

申请日：2007-12-31

申请人： Paul Paternoster ,  Vaibhavi Sabharanjak ,  Po-Shen Lai

发明人： Paul Paternoster ,  Vaibhavi Sabharanjak ,  Po-Shen Lai

IPC分类号： G06F17/50

CPC分类号： H01L23/60 ,  H01L23/552 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/4917 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01031 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2224/45099 ,  H01L2924/00

摘要： An integrated circuit (IC) having a selectively-designated electromagnetic compatibility (EMC) performance characteristic. The IC includes an IC die having an input or output (I/O) node. A first I/O cell of a first type associated with the I/O node provides a first EMC performance characteristic, and a second I/O cell of a second type associated with the I/O node provides a second EMC performance characteristic different from the first EMC performance characteristic. A first bonding pad is electrically coupled with the first I/O cell, and a second bonding pad is electrically coupled with the second I/O cell. The IC die can be packaged into a packaged IC having an I/O pin corresponding to the I/O node. The I/O pin is wired to one of either the first bonding pad or the second bonding pad, but not to the other, such that a pinout for the I/O node is preferentially provided having one of either the first EMC performance characteristic or the second EMC performance characteristic.

摘要翻译： 具有选择性地指定的电磁兼容性（EMC）性能特性的集成电路（IC）。 IC包括具有输入或输出（I / O）节点的IC管芯。 与I / O节点相关联的第一类型的第一个I / O单元提供了第一个EMC性能特性，并且与I / O节点相关联的第二类型的第二I / O单元提供了与 第一个EMC性能特点。 第一接合焊盘与第一I / O单元电耦合，并且第二接合焊盘与第二I / O单元电耦合。 IC芯片可以封装成具有对应于I / O节点的I / O引脚的封装IC。 I / O引脚连接到第一焊盘或第二接合焊盘中的一个，但不连接到另一个，使得优先提供用于I / O节点的引脚排列，其具有第一EMC性能特性之一或 第二个EMC性能特点。

公开(公告)号：US07928746B1

公开(公告)日：2011-04-19

申请号：US11966147

申请日：2007-12-28

申请人： Po-Shen Lai ,  Paul A. Lassa ,  Paul C. Paternoster

发明人： Po-Shen Lai ,  Paul A. Lassa ,  Paul C. Paternoster

IPC分类号： G01R31/3187

CPC分类号： G01R31/2884 ,  G01R31/318511 ,  G01R31/318558 ,  G01R31/31924

摘要： A multi-interface integrated circuit in which, during the chip's lifetime in use, only one interface is active at a time. However, special test logic powers up all of the on-chip interface modules at once, so that a complete test cycle can be performed. All of the interfaces are exercised in one test program. Since some pads are inactive in some interface modes, mask bits are used to select which pads are monitored during which test cycles.

摘要翻译： 一种多接口集成电路，其中在芯片使用寿命期间，一次只有一个接口处于活动状态。 但是，特殊的测试逻辑可以一次启动所有片上接口模块，从而可以执行完整的测试周期。 所有接口都在一个测试程序中执行。 由于某些接口模式下某些焊盘无效，因此使用掩码位来选择在哪个测试周期内监视哪些焊盘。

公开(公告)号：US06542512B1

公开(公告)日：2003-04-01

申请号：US09346745

申请日：1999-07-02

申请人： Jenny Liu Fischer ,  Ching Yu ,  Jerry Chun-Jen Kuo ,  Po-Shen Lai ,  Autumn Jane Niu ,  Ian Lam

发明人： Jenny Liu Fischer ,  Ching Yu ,  Jerry Chun-Jen Kuo ,  Po-Shen Lai ,  Autumn Jane Niu ,  Ian Lam

IPC分类号： H04L1228

CPC分类号： H04L49/901 ,  H04L47/50 ,  H04L49/3027 ,  H04L49/351 ,  H04L49/90

摘要： A network switch in a packet switched network includes a plurality of network switch ports, each configured for sending and receiving data packets between a medium interface and the network switch. The network switch port includes an IEEE 802.3 compliant transmit state machine and receive state machine configured for transmitting and receiving network data to and from a medium interface, such as a reduced medium independent interface, respectively. The network switch port also includes a memory management unit configured for selectively transferring the network data between the transmit and receive state machines and a random access transmit buffer and a random access receive buffer, respectively. The transmit state machine outputs a flush transmit buffer signal to the transmit memory management unit in response to a detected error in transmitting the transmit data. The transmit memory management unit, in response to the flush transmit buffer signal, sets an incremented transmit buffer pointer value to a buffer pointer value corresponding to a next transmit data stored in the transmit buffer.

摘要翻译： 分组交换网络中的网络交换机包括多个网络交换机端口，每个网络交换机端口被配置为在介质接口和网络交换机之间发送和接收数据分组。 网络交换机端口包括符合IEEE 802.3标准的传输状态机和接收状态机，其配置用于分别向介质接口（例如简化介质独立接口）发送和接收网络数据。 网络交换机端口还包括配置用于分别在发送和接收状态机与随机接入发送缓冲器和随机接入接收缓冲器之间选择性地传送网络数据的存储器管理单元。 发送状态机响应于发送发送数据中检测到的错误，向发送存储器管理单元输出清空发送缓冲器信号。 发送存储器管理单元响应于刷新发送缓冲器信号，将增加的发送缓冲器指针值设置为对应于存储在发送缓冲器中的下一个发送数据的缓冲器指针值。

公开(公告)号：US6128308A

公开(公告)日：2000-10-03

申请号：US993063

申请日：1997-12-18

申请人： Jerry Chun-Jen Kuo ,  Autumn Jane Niu ,  Po-Shen Lai

发明人： Jerry Chun-Jen Kuo ,  Autumn Jane Niu ,  Po-Shen Lai

IPC分类号： H04L12/413 ,  H04L12/56 ,  H04L12/54

CPC分类号： H04L49/901 ,  H04L49/90

摘要： A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memory between the read and write controllers. The synchronization circuit determines the presence of a stored frame in the random access memory by asynchronously comparing write counter and read counter values stored in gray code counters, where each counter is configured for changing a single bit of a counter value in response to an increment signal. Use of gray code counters enables asynchronous comparisons to be made between the two counter values, independent of the host computer bus clock domain and the network clock domain.

摘要翻译： 网络接口设备包括用作发送和接收缓冲器的随机存取存储器，用于在主计算机总线和分组交换网络之间传输和接收数据帧。 网络接口设备包括用于每个发送和接收缓冲器的读和写控制器，其中每个写控制器在与相应的读控制器分离的时钟域中操作。 存储器管理单元还包括同步电路，其控制仲裁以访问读取和写入控制器之间的随机存取存储器。 同步电路通过异步比较存储在灰度代码计数器中的写入计数器和读取计数器值来确定随机存取存储器中存储的帧的存在，其中每个计数器被配置为响应于增量信号来改变计数器值的单个位 。 使用灰色代码计数器可以在两个计数器值之间进行异步比较，与主机总线时钟域和网络时钟域无关。

公开(公告)号：US08135944B2

公开(公告)日：2012-03-13

申请号：US11686350

申请日：2007-03-14

申请人： Paul Lassa ,  Paul Paternoster ,  Po-Shen Lai ,  Yongliang Wang

发明人： Paul Lassa ,  Paul Paternoster ,  Po-Shen Lai ,  Yongliang Wang

IPC分类号： H01R24/00

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  Y02D10/171 ,  Y10S439/93 ,  Y10S439/945

摘要： A plurality of separately powered data interface circuits, a controller circuit, and power switch circuits that collectively enable a supply of power to only one of the data interface circuits and disable the supply of power to the other data interface circuits. Alternatively, the separately powered circuits need not be data interface circuits.

摘要翻译： 多个单独供电的数据接口电路，控制器电路和功率开关电路，其共同地仅向数据接口电路之一提供电力，并且禁止向其它数据接口电路供电。 或者，单独供电的电路不需要是数据接口电路。

公开(公告)号：US20110283055A1

公开(公告)日：2011-11-17

申请号：US13089093

申请日：2011-04-18

申请人： Po-Shen Lai ,  Paul A. Lassa ,  Paul C. Paternoster

发明人： Po-Shen Lai ,  Paul A. Lassa ,  Paul C. Paternoster

IPC分类号： G06F12/00

CPC分类号： G01R31/2884 ,  G01R31/318511 ,  G01R31/318558 ,  G01R31/31924

摘要： A multi-interface integrated circuit in which, during the chip's lifetime in use, only one interface is active at a time. However, special test logic powers up all of the on-chip interface modules at once, so that a complete test cycle can be performed. All of the interfaces are exercised in one test program. Since some pads are inactive in some interface modes, mask bits are used to select which pads are monitored during which test cycles.

摘要翻译： 一种多接口集成电路，其中在芯片使用寿命期间，一次只有一个接口处于活动状态。 但是，特殊的测试逻辑可以一次启动所有片上接口模块，从而可以执行完整的测试周期。 所有接口都在一个测试程序中执行。 由于某些接口模式下某些焊盘无效，因此使用掩码位来选择在哪个测试周期内监视哪些焊盘。