公开(公告)号：US20060008075A1

公开(公告)日：2006-01-12

申请号：US10886373

申请日：2004-07-07

Applicant: Jeffrey Scott ,  Navdeep Sooch ,  David Welland

Inventor： Jeffrey Scott ,  Navdeep Sooch ,  David Welland

IPC: H04M1/00

CPC classification number: H04M1/738 ,  H04M11/062

Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. A bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information. Finally, the isolation system may include a pulse transformer to accommodate ADSL circuitry, whereby power is transmitted through the pulse transformer.

Abstract translation: 提供了一种适用于电话，医疗仪器，工业过程控制和其他应用的隔离系统。 本发明的优选实施例包括电容隔离屏障，通过数字信号传送数字信号。 该系统提供跨越隔离屏障的通信手段，其高度免疫幅度和相位噪声干扰。 可以在隔离屏障的一侧采用时钟恢复电路，从跨屏障通信的数字信号提取定时信息，并且滤除在屏障处引入的相位噪声的影响。 Δ-Σ转换器可以设置在隔离屏障的两侧以在模拟和数字域之间转换信号。 隔离电源也可以设置在屏障的隔离侧上，由此响应于穿过隔离屏障接收的数字数据产生直流电流。 提供了双向隔离系统，由此使用单对隔离电容器实现数字信号的双向通信。 在优选实施例中，跨屏障通信的数字数据由与其他数字控制，信令和成帧信息在时间上多路复用的数字delta-sigma数据信号组成。 最后，隔离系统可以包括用于容纳ADSL电路的脉冲变压器，由此通过脉冲变压器传输功率。

公开(公告)号：US07720176B2

公开(公告)日：2010-05-18

申请号：US11510339

申请日：2006-08-25

Applicant: David Welland

Inventor： David Welland

IPC: H04L27/12

CPC classification number: H04L27/0008 ,  H04B1/04

Abstract: In one embodiment, the present invention includes an apparatus having multiple transmission paths, including a first transmission path configured to receive and process baseband data in a first mode of operation to generate a radio frequency (RF) signal for output via a common output path, and a second transmission path configured to receive and process the baseband data in a second mode of operation to generate the RF signal for output via the common output path.

Abstract translation: 在一个实施例中，本发明包括具有多个传输路径的设备，包括：第一传输路径，其被配置为在第一操作模式中接收和处理基带数据，以产生用于经由公共输出路径输出的射频（RF）信号; 以及第二传输路径，其被配置为在第二操作模式中接收和处理所述基带数据，以产生所述RF信号以经由所述公共输出路径输出。

公开(公告)号：US20060284746A1

公开(公告)日：2006-12-21

申请号：US11461408

申请日：2006-07-31

Applicant: Yunteng Huang ,  Bruno Garlepp ,  David Welland

Inventor： Yunteng Huang ,  Bruno Garlepp ,  David Welland

IPC: H03M7/00

CPC classification number: H03L7/093 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L2207/06 ,  H03M7/3011 ,  H03M7/3028 ,  H03M7/3037

Abstract: An exemplary PLL circuit includes a VCO responsive to a plurality of sub-varactor control signals. A digital loop filter for the PLL digitally generates a varactor control word, which is digitally expanded into a plurality of digital values, each of which is conveyed to a corresponding one of a plurality of DACs. A multiplexer is configured to respectively convey the DAC output signals to a group of sub-varactor control signals according to the varactor control word, and to drive remaining sub-varactor control signals to either the full-scale high value or the full-scale low value of the DAC outputs. Each of the DACs preferably includes a hybrid first order/second order sigma-delta modulator, and in certain embodiments, a NRZ-to-RZ coder circuit, and a linear filter circuit.

Abstract translation: 示例性PLL电路包括响应于多个子变容二极管控制信号的VCO。 用于PLL的数字环路滤波器数字地生成变容二极管控制字，其被数字地扩展成多个数字值，每个数字值被传送到多个DAC中的对应的一个。 复用器被配置为根据变容二极管控制字将DAC输出信号分别传送到一组子变容二极管控制信号，并且将剩余的子变容二极管控制信号驱动到满量程高值或满量程低 DAC输出的值。 每个DAC优选地包括混合一阶/二阶Σ-Δ调制器，并且在某些实施例中，NRZ至RZ编码器电路和线性滤波器电路。

公开(公告)号：US20060003728A1

公开(公告)日：2006-01-05

申请号：US10880483

申请日：2004-06-30

Applicant: G. Tuttle ,  David Welland ,  Scott Willingham

Inventor： G. Tuttle ,  David Welland ,  Scott Willingham

IPC: H04B1/28

CPC classification number: H04B1/30

Abstract: A ratiometric clock system for an integrated receiver and associated method are disclosed that provide an advantageous solution for combining digital signal processing (DSP) circuitry on the same integrated circuit as mixer and local oscillator (LO) generation circuitry. The generation circuitry generates an oscillation signal that is passed through a first divider to generate mixing signals for the mixer and that is passed through a second divider to generate a digital clock signal that is utilized by the DSP circuitry. This digital clock signal can be utilized by integrated analog-to-digital conversion circuitry, as well.

Abstract translation: 公开了一种用于集成接收机和相关方法的比例时钟系统，其提供用于将数字信号处理（DSP）电路组合在与混频器和本地振荡器（LO）生成电路相同的集成电路上的有利解决方案。 产生电路产生振荡信号，该信号通过第一分频器以产生用于混频器的混频信号，并通过第二分频器产生由DSP电路利用的数字时钟信号。 该数字时钟信号也可以由集成的模数转换电路使用。

公开(公告)号：US20050195037A1

公开(公告)日：2005-09-08

申请号：US11022560

申请日：2004-12-22

Applicant: Timothy Dupuis ,  David Welland ,  Susanne Paul ,  Ali Niknejad

Inventor： Timothy Dupuis ,  David Welland ,  Susanne Paul ,  Ali Niknejad

IPC: H03F3/217 ,  H03K17/0416 ,  H03K17/687 ,  H03G3/10

CPC classification number: H03F3/2173 ,  H01L23/645 ,  H01L2223/6644 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H03F3/195 ,  H03F3/2176 ,  H03F3/30 ,  H03F3/72 ,  H03K17/04163 ,  H03K17/6872 ,  H01L2224/0401

Abstract: A method and apparatus is provided for detecting the output power of a power amplifier. The output power is detected by detecting the absolute values of the voltage and current at the output of the amplifier and mixing the detected voltage and current to generate a signal related to the output power.

Abstract translation: 提供了一种用于检测功率放大器的输出功率的方法和装置。 通过检测放大器输出端的电压和电流的绝对值来检测输出功率，并混合检测的电压和电流以产生与输出功率有关的信号。

公开(公告)号：US07697901B2

公开(公告)日：2010-04-13

申请号：US11394249

申请日：2006-03-30

Applicant: Srinath Sridharan ,  Ahmed Emira ,  Aria Eshraghi ,  David Welland

Inventor： Srinath Sridharan ,  Ahmed Emira ,  Aria Eshraghi ,  David Welland

IPC: H01Q11/12 ,  H04B1/04

CPC classification number: H04B1/0475

Abstract: A method includes controlling a mixer gain to provide a range of selected power output levels from the mixer using a first control scheme for a low portion of the range and using a second control scheme for a high portion of the range. Using the selected mixer gain, incoming baseband signals may be upconverted in the mixer to a transmission frequency and output from the mixer at the selected power output level.

Abstract translation: 一种方法包括：控制混频器增益，以使用第一控制方案从该混频器提供所选择的功率输出电平的范围，并对该范围的高部分使用第二控制方案。 使用所选择的混频器增益，输入基带信号可以在混频器中上变频到传输频率，并在所选功率输出电平下从混频器输出。

公开(公告)号：US20050036604A1

公开(公告)日：2005-02-17

申请号：US10629480

申请日：2004-10-28

Applicant: Jeffrey Scott ,  Navdeep Sooch ,  David Welland

Inventor： Jeffrey Scott ,  Navdeep Sooch ,  David Welland

IPC: C09K8/32 ,  H04L7/033 ,  H04L25/06 ,  H04M11/06 ,  H04M1/00 ,  H04M9/00

CPC classification number: H04L25/0266 ,  C09K8/32 ,  H04L7/033 ,  H04L25/06 ,  H04M11/06

Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. A bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information. Finally, the isolation system may include a pulse transformer to accommodate ADSL circuitry, whereby power is transmitted through the pulse transformer.

Abstract translation: 提供了一种适用于电话，医疗仪器，工业过程控制和其他应用的隔离系统。 本发明的优选实施例包括电容隔离屏障，通过数字信号传送数字信号。 该系统提供跨越隔离屏障的通信手段，其高度免疫幅度和相位噪声干扰。 可以在隔离屏障的一侧采用时钟恢复电路，从跨屏障通信的数字信号提取定时信息，并且滤除在屏障处引入的相位噪声的影响。 Δ-Σ转换器可以设置在隔离屏障的两侧以在模拟和数字域之间转换信号。 隔离电源也可以设置在屏障的隔离侧上，由此响应于穿过隔离屏障接收的数字数据产生直流电流。 提供了双向隔离系统，由此使用单对隔离电容器实现数字信号的双向通信。 在优选实施例中，跨屏障通信的数字数据由与其他数字控制，信令和成帧信息在时间上多路复用的数字delta-sigma数据信号组成。 最后，隔离系统可以包括用于容纳ADSL电路的脉冲变压器，由此通过脉冲变压器传输功率。

公开(公告)号：US08193822B2

公开(公告)日：2012-06-05

申请号：US12494417

申请日：2009-06-30

Applicant: David Welland

Inventor： David Welland

IPC: G01R27/26

CPC classification number: G01R27/2605 ,  H03K17/9622

Abstract: A circuit for determining a value of a variable capacitor includes first circuitry for generating a first indication when a variable voltage across the variable capacitor exceeds a threshold voltage. Second circuitry generates a second indication when a reference voltage across a reference capacitor exceeds the threshold voltage. Control logic responsive to the first and second indications generate a control signal indicating whether the first indication or the second indication occurs first. A successive approximation engine generates an N-bit control value responsive to the control signal. A variable current source is responsive to the N-bit control value for generating a variable current to the first circuitry. A reference current source generates a reference current to the second circuitry.

Abstract translation: 用于确定可变电容器的值的电路包括当可变电容器两端的可变电压超过阈值电压时产生第一指示的第一电路。 当参考电容两端的参考电压超过阈值电压时，第二电路产生第二指示。 响应于第一和第二指示的控制逻辑产生指示第一指示或第二指示是否首先出现的控制信号。 逐次逼近引擎响应于控制信号产生N位控制值。 可变电流源响应于N位控制值以产生到第一电路的可变电流。 参考电流源产生到第二电路的参考电流。

公开(公告)号：US20120054379A1

公开(公告)日：2012-03-01

申请号：US12870849

申请日：2010-08-30

Applicant: Kafai Leung ,  Brent Wilson ,  Yonghong Tao ,  Shan Wang ,  Shantonu Bhadury ,  Suby Pellissery ,  Raghavendra Pai Kateel ,  David Welland ,  David Andreas ,  Gabriel Vogel

Inventor： Kafai Leung ,  Brent Wilson ,  Yonghong Tao ,  Shan Wang ,  Shantonu Bhadury ,  Suby Pellissery ,  Raghavendra Pai Kateel ,  David Welland ,  David Andreas ,  Gabriel Vogel

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F1/3206 ,  G06F1/3262 ,  G06F1/3275 ,  G06F3/0416 ,  G06F3/044 ,  G06F2203/04104 ,  Y02D10/13 ,  Y02D10/14

Abstract: An integrated control circuit is disclosed including a central processing unit operating in a normal full system power mode and in a reduced system low power mode, and a memory. A plurality of peripheral units are provided, at least one of which includes an input/output for interfacing with at least an external system for receiving information therefrom and a process block. The process block processes the received information from the external system and during the processing of the received information, data is stored in the at least one peripheral unit, and data is transferred at least to or at least from the memory. The input/output and process blocks are fully operable in the full system power mode and the reduced system power mode. A direct memory access (DMA) transfers data directly between the at least one peripheral and the memory when such data transfer is required by the peripheral. The DMA operates in a full power DMA mode when data transfer is required and a low power DMA mode when data transfer is not required. The central processing unit is operable, in the normal full system power mode, to interface with the memory and with the at least one peripheral unit to access data stored by the at least one peripheral unit.

Abstract translation: 公开了一种集成控制电路，其包括以正常全系统功率模式和降低的系统低功率模式操作的中央处理单元和存储器。 提供多个外围单元，其中至少一个包括用于与至少外部系统进行接口以从其接收信息的输入/输出和处理块。 处理块处理来自外部系统的接收到的信息，并且在接收到的信息的处理期间，将数据存储在至少一个外围单元中，并且数据至少传送到或至少从存储器传送。 输入/输出和过程模块可以在全系统电源模式和降低的系统电源模式下完全工作。 直接存储器访问（DMA）在外围设备需要这种数据传输时，直接在至少一个外围设备和存储器之间传输数据。 当需要数据传输时，DMA工作在全功率DMA模式，而在不需要数据传输时，DMA工作在低功耗DMA模式。 中央处理单元在正常全系统功率模式下可操作地与存储器和至少一个外围单元接口以访问由至少一个外围单元存储的数据。

公开(公告)号：US20050242897A1

公开(公告)日：2005-11-03

申请号：US11146337

申请日：2005-06-06

Applicant: Lysander Lim ,  David Welland ,  John Pavelka ,  Edmund Healy

Inventor： Lysander Lim ,  David Welland ,  John Pavelka ,  Edmund Healy

IPC: H01L23/66 ,  H03B5/00 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L7/199

CPC classification number: H03L7/10 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H03L7/099 ,  H03L7/18 ,  H03L7/199 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: A semiconductor package includes a package substrate and an integrated circuit. The package substrate has a first surface. The integrated circuit couples electrically to the first surface of the package substrate. The integrated circuit and the package substrate together form the semiconductor package. The semiconductor package also includes a first inductance circuit and a second inductance circuit, both formed within the semiconductor package. The first and second inductance circuits couple to each other in parallel. The first and second inductance circuits have substantially symmetrical geometric characteristics.

Abstract translation: 半导体封装包括封装基板和集成电路。 封装基板具有第一表面。 集成电路电耦合到封装衬底的第一表面。 集成电路和封装衬底一起形成半导体封装。 半导体封装还包括形成在半导体封装内的第一电感电路和第二电感电路。 第一和第二电感电路并联耦合。 第一和第二电感电路具有基本对称的几何特性。