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11.发明申请Strained silicon on relaxed sige film with uniform misfit dislocation density 有权应变硅在轻松的超薄膜上具有均匀的失配位错密度公开(公告)号：US20050164477A1
公开(公告)日：2005-07-28
申请号：US11048739
申请日：2005-02-03
IPC分类号： H01L21/205 , C30B1/00 , H01L21/20 , H01L21/265 , H01L21/322 , H01L21/324 , H01L21/36 , H01L29/10
CPC分类号： H01L21/26506 , H01L21/324 , H01L29/1054
摘要： A method for forming a semiconductor substrate structure is provided. A compressively strained SiGe layer is formed on a silicon substrate. Atoms are ion-implanted onto the SiGe layer to cause end-of-range damage. Annealing is performed to relax the strained SiGe layer. During the annealing, interstitial dislocation loops are formed as uniformly distributed in the SiGe layer. The interstitial dislocation loops provide a basis for nucleation of misfit dislocations between the SiGe layer and the silicon substrate. Since the interstitial dislocation loops are distributed uniformly, the misfit locations are also distributed uniformly, thereby relaxing the SiGe layer. A tensilely strained silicon layer is formed on the relaxed SiGe layer.
摘要翻译： 提供一种形成半导体衬底结构的方法。 在硅衬底上形成压缩应变SiGe层。 原子被离子注入SiGe层以造成范围内的损伤。 进行退火以松弛应变的SiGe层。 在退火过程中，间隙位错环形成均匀分布在SiGe层中。 间隙位错环为SiGe层和硅衬底之间的失配位错的成核提供了基础。 由于间隙位错环分布均匀，因此错位位置也均匀分布，从而松弛SiGe层。 在松弛的SiGe层上形成拉伸应变硅层。
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12.发明申请公开(公告)号：US20050148134A1
公开(公告)日：2005-07-07
申请号：US11070113
申请日：2005-03-02
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823814
摘要： The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETs, by implanting in the sources and drains of the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.
摘要翻译： CMOS电路的速度通过在NFET上施加纵向拉伸应力和PFET上的纵向压缩应力，通过将元素周期表第八列中的NFET离子的源和漏极注入氢中并将其植入到 来自周期表第四和第六列的PFET离子的源极和漏极。
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13.发明申请Method and structure for improved MOSFETs using poly/silicide gate height control 失效使用多晶硅/硅化物栅极高度控制的改进MOSFET的方法和结构公开(公告)号：US20050145950A1
公开(公告)日：2005-07-07
申请号：US11057126
申请日：2005-02-15
IPC分类号： H01L21/8238 , H01L21/84 , H01L29/76
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L21/84
摘要： A method for manufacturing an integrated circuit that has a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor. This method involves depositing oxide fill on the n-type transistor and the p-type transistor and chemical/mechanical polishing the deposited oxide fill such that a gate stack of the n-type transistor and a gate stack of the p-type transistor, which each have spacers which are surrounded with oxide. The method further involves etching a portion of the polysilicon from a gate of the p-type field effect transistor, depositing a low resistance material (e.g., Co, Ni, Ti, or other similar metals) on the n-type field effect transistor and the p-type field effect transistor, and heating the integrated circuit such that the deposited material reacts with the polysilicon of the n-type transistor and the polysilicon of the p-type transistor to form silicide. The silicide formed on the p-type polysilicon imposes compressive mechanical stresses along the longitudinal direction of the channel of the p-type field effect transistor. A semiconductor device formed by this method has compressive stresses along the length of the PFET channel and tensile stresses along the length of the NFET channel.
摘要翻译： 一种具有包括n型场效应晶体管和p型场效应晶体管的多个半导体器件的集成电路的制造方法。 该方法包括在n型晶体管和p型晶体管上沉积氧化物填充物，并化学/机械抛光沉积的氧化物填充物，使得n型晶体管的栅极堆叠和p型晶体管的栅极堆叠，其中 每个具有被氧化物包围的间隔物。 该方法还包括从p型场效应晶体管的栅极蚀刻多晶硅的一部分，在n型场效应晶体管上沉积低电阻材料（例如，Co，Ni，Ti或其它类似的金属），以及 p型场效应晶体管，并且加热集成电路，使得沉积的材料与n型晶体管的多晶硅和p型晶体管的多晶硅反应以形成硅化物。 形成在p型多晶硅上的硅化物沿着p型场效应晶体管的沟道的纵向施加压缩机械应力。 通过该方法形成的半导体器件具有沿着PFET沟道的长度的压缩应力和沿着NFET沟道的长度的拉伸应力。
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公开(公告)号：US20050130358A1
公开(公告)日：2005-06-16
申请号：US10733378
申请日：2003-12-12
IPC分类号： H01L21/76 , H01L21/20 , H01L21/336 , H01L21/762 , H01L21/8238 , H01L21/84 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/786 , H01L21/8234 , H01L29/739 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/785 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/7842 , H01L29/78684
摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material form a first island and second island at an pFET region and a nFET region, respectively. A tensile hard mask is formed on the first and the second island layer prior to forming finFETs. An Si epitaxial layer is grown on the sidewalls of the finFETs with the hard mask, now a capping layer which is under tension, preventing lateral buckling of the NFET fin.
摘要翻译： 提供半导体结构和制造方法。 制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。 第一材料和第二材料分别在pFET区和nFET区形成第一岛和第二岛。 在形成finFET之前，在第一和第二岛层上形成拉伸硬掩模。 在具有硬掩模的finFET的侧壁上生长Si外延层，现在是处于张力下的封盖层，防止NFET鳍片的横向屈曲。
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公开(公告)号：US20050245017A1
公开(公告)日：2005-11-03
申请号：US11175223
申请日：2005-07-07
IPC分类号： H01L21/20 , H01L21/28 , H01L21/302 , H01L21/336 , H01L21/44 , H01L21/461 , H01L21/4763 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/72 , H01L29/78 , H01L29/786 , H01L31/062
CPC分类号： H01L29/7845 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/4908 , H01L29/66795 , H01L29/785
摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.
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16.发明申请Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby 失效具有T形翅片的FinFET器件的制造方法和由此制造的器件公开(公告)号：US20050191795A1
公开(公告)日：2005-09-01
申请号：US10790550
申请日：2004-03-01
IPC分类号： H01L21/335 , H01L21/336 , H01L21/8242 , H01L29/772 , H01L29/786
CPC分类号： H01L29/7853 , H01L29/66795 , H01L29/7842
摘要： An FET device comprises a semiconductor structure with a source island, a drain island over a horizontal surface of a substrate comprising an insulating material. A channel structure over the horizontal surface of the substrate connects between the drain and the source, with the channel structure comprising a horizontal semiconductor channel fin above a vertical fin with the planar fin and the vertical fin having a T-shaped cross-section. The vertical fin is contact with the horizontal surface of the substrate and the planar fin is in contact with the top of the vertical fin. A gate dielectric layer covers exposed surfaces of the channel structure. A gate electrode straddles the channel gate dielectric and the channel structure. Then a sacrificial layer such as SiGe is deposited upon the substrate before forming the vertical fin which may be either a semiconductor or dielectric material. The planar fin is a semiconductor material such as Si, SiGe or Ge.
摘要翻译： FET器件包括具有源岛的半导体结构，在包括绝缘材料的衬底的水平表面上的漏极岛。 衬底的水平表面上的沟道结构连接在漏极和源极之间，其中沟道结构包括在具有平面翅片的垂直翅片上方的水平半导体沟道翅片，并且垂直翅片具有T形横截面。 垂直翅片与基板的水平表面接触，并且平面翅片与垂直翅片的顶部接触。 栅介质层覆盖通道结构的暴露表面。 栅电极横跨沟道栅极电介质和沟道结构。 然后在形成可以是半导体或电介质材料的垂直翅片之前，将诸如SiGe的牺牲层沉积在衬底上。 平面翅片是诸如Si，SiGe或Ge的半导体材料。
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公开(公告)号：US20050145992A1
公开(公告)日：2005-07-07
申请号：US11057129
申请日：2005-02-15
IPC分类号： H01L21/265 , H01L21/332 , H01L21/336 , H01L21/461 , H01L21/8234 , H01L21/8238 , H01L29/10 , H01L29/78 , H01L31/117
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/26513 , H01L29/1054 , H01L29/6656
摘要： The first source and drain regions are formed in an upper surface of a SiGe substrate. The first source and drain regions containing an N type impurity. Vacancy concentration in the first source and drain regions are reduced in order to reduce diffusion of the N type impurity contained In the first source and drain regions. The vacancy concentration Is reduced by an interstitial element or a vacancy-trapping element in the first source and drain regions. The interstitial element or the vacancy-trapping element is provided by ion-implantation.
摘要翻译： 第一源区和漏区形成在SiGe衬底的上表面中。 含有N型杂质的第一源区和漏区。 减少第一源区和漏区中的空位浓度，以便减少在第一源区和漏区中含有的N型杂质的扩散。 空位浓度通过第一源极和漏极区域中的间隙元素或空穴捕获元素而减小。 间隙元素或空位捕获元件通过离子注入提供。
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18.发明申请公开(公告)号：US20050142788A1
公开(公告)日：2005-06-30
申请号：US11065061
申请日：2005-02-25
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12 , H01L29/06 , H01L21/331 , H01L21/8222 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L21/84 , H01L21/7624 , H01L27/1203 , H01L29/7849
摘要： A method for manufacturing a semiconductor device is provided. The method includes forming a semiconductor layer on a substrate. The first region of the substrate is expanded to push up the first portion of the semiconductor layer, thereby applying tensile stress to the first portion. The second region of the substrate is compressed to pull down the second portion of the semiconductor layer, thereby applying compressive stress to the second portion. An N type device is formed over the first portion of the semiconductor layer, and a P type device is formed over the second portion of the semiconductor layer.
摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在衬底上形成半导体层。 衬底的第一区域被膨胀以向上推动半导体层的第一部分，从而对第一部分施加拉伸应力。 衬底的第二区域被压缩以拉下半导体层的第二部分，从而向第二部分施加压应力。 在半导体层的第一部分上形成N型器件，并且在半导体层的第二部分上形成P型器件。
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19.发明申请Structure and method to improve channel mobility by gate electrode stress modification 有权通过栅电极应力改变来提高沟道迁移率的结构和方法公开(公告)号：US20050093059A1
公开(公告)日：2005-05-05
申请号：US10695752
申请日：2003-10-30
IPC分类号： H01L21/20 , H01L21/28 , H01L21/302 , H01L21/336 , H01L21/44 , H01L21/461 , H01L21/4763 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/72 , H01L29/78 , H01L29/786 , H01L31/062
CPC分类号： H01L29/7845 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/4908 , H01L29/66795 , H01L29/785
摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and PFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.
摘要翻译： 在制造包括nFET和PFET的互补金属氧化物半导体（CMOS）场效应晶体管的情况下，通过使栅电极的材料与金属反应来增强或调节载流子迁移率，以产生应力合金（优选CoSi 2Si，NiSi或PdSi）。 在nFET和pFET两者的情况下，各合金的固有应力对相应晶体管的沟道产生相反的应力。 通过在nFET和pFET合金或硅化物中保持相反的应力，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。
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公开(公告)号：US20050054145A1
公开(公告)日：2005-03-10
申请号：US10605108
申请日：2003-09-09
IPC分类号： H01L21/265 , H01L21/332 , H01L21/336 , H01L21/461 , H01L21/8234 , H01L21/8238 , H01L29/10 , H01L29/78 , H01L31/117
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/26513 , H01L29/1054 , H01L29/6656
摘要： The first source and drain regions are formed in an upper surface of a SiGe substrate. The first source and drain regions containing an N type impurity. Vacancy concentration in the first source and drain regions are reduced in order to reduce diffusion of the N type impurity contained in the first source and drain regions. The vacancy concentration is reduced by an interstitial element or a vacancy-trapping element in the first source and drain regions. The interstitial element or the vacancy-trapping element is provided by ion-implantation.
摘要翻译： 第一源区和漏区形成在SiGe衬底的上表面中。 含有N型杂质的第一源区和漏区。 为了减少包含在第一源极和漏极区域中的N型杂质的扩散，第一源区和漏区中的空位浓度被降低。 空位浓度通过第一源极和漏极区域中的间隙元素或空穴捕获元件而减小。 间隙元素或空位捕获元件通过离子注入提供。
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