公开(公告)号：US20140281336A1

公开(公告)日：2014-09-18

申请号：US13982807

申请日：2013-03-13

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT, LLC

Inventor： Yan Solihin

IPC: G06F12/02

CPC classification number: G06F12/0292 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0673 ,  G06F12/0223 ,  G06F12/023

Abstract: Technologies are generally described for methods and systems effective to implement a memory allocation accelerator. A processor may generate a request for allocation of a requested chunk of memory. The request may be received by a memory allocation accelerator configured to be in communication with the processor. The memory allocation accelerator may process the request to identify an address for a particular chunk of memory corresponding to the request and may return the address to the processor.

Abstract translation: 通常描述有效实现内存分配加速器的方法和系统的技术。 处理器可以产生对所请求的存储器块的分配的请求。 该请求可以被配置为与处理器通信的存储器分配加速器来接收。 存储器分配加速器可以处理该请求以识别与该请求对应的特定存储块的地址，并且可以将该地址返回给处理器。

公开(公告)号：US20140026148A1

公开(公告)日：2014-01-23

申请号：US14035177

申请日：2013-09-24

Applicant: Empire Technology Development LLC

Inventor： Yan Solihin

IPC: G06F9/30 ,  G06F9/52

CPC classification number: G06F9/30043 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3851 ,  G06F9/4893 ,  G06F9/52 ,  Y02D10/24

Abstract: Technologies for low power execution of one or more threads of a multithreaded program by one or more processing elements are generally disclosed.

Abstract translation: 通常公开了由一个或多个处理元件执行多线程程序的一个或多个线程的低功率执行的技术。

公开(公告)号：US09990293B2

公开(公告)日：2018-06-05

申请号：US14457128

申请日：2014-08-12

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Yan Solihin

IPC: G06F12/08 ,  G06F12/12 ,  G11C7/10 ,  G06F12/0831 ,  G06F12/0811 ,  G11C11/401 ,  G11C11/406 ,  G06F12/123

CPC classification number: G06F12/0833 ,  G06F12/0811 ,  G06F12/123 ,  G06F2212/1024 ,  G11C7/1072 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40622 ,  Y02D10/13

Abstract: Techniques described herein generally include methods and systems related to improving energy efficiency in a chip multiprocessor by reducing the energy consumption of a DRAM cache for such a multi-chip processor. Methods of varying refresh interval may be used to improve the energy efficiency of such a DRAM cache. Specifically, a per-set refresh interval based on retention time of memory blocks in the set may be determined, and, starting from the leakiest memory block, memory blocks stored in the DRAM cache that are associated with data also stored in a lower level of cache are not refreshed.

公开(公告)号：US09760486B2

公开(公告)日：2017-09-12

申请号：US15080605

申请日：2016-03-25

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Yan Solihin

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0804 ,  G06F12/0817 ,  G06F9/46 ,  G06F12/0806 ,  G06F12/123 ,  G06F9/48

CPC classification number: G06F12/0804 ,  G06F9/461 ,  G06F9/4856 ,  G06F12/0806 ,  G06F12/0817 ,  G06F12/123 ,  G06F2212/62

Abstract: Technologies are generally described herein for accelerating a cache state transfer in a multicore processor. The multicore processor may include first, second, and third tiles. The multicore processor may initiate migration of a thread executing on the first core at the first tile from the first tile to the second tile. The multicore processor may determine block addresses of blocks to be transferred from a first cache at the first tile to a second cache at the second tile, and identify that a directory at the third tile corresponds to the block addresses. The multicore processor may update the directory to reflect that the second cache shares the blocks. The multicore processor may transfer the blocks from the first cache in the first tile to the second cache in the second tile effective to complete the migration of the thread from the first tile to the second tile.

公开(公告)号：US09632832B2

公开(公告)日：2017-04-25

申请号：US14758404

申请日：2014-02-27

Applicant: Empire Technology Development LLC

Inventor： Yan Solihin

IPC: G06F9/50 ,  G06F12/08 ,  G06F12/0806 ,  G06F12/0875

CPC classification number: G06F9/5033 ,  G06F9/4881 ,  G06F9/5027 ,  G06F11/34 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0875 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62

Abstract: Technologies are generally described for methods and systems to assign threads in a multi-core processor. In an example, a method to assign threads in a multi-core processor may include determining data relating to memory controllers fetching data in response to cache misses experienced by a first core and a second core. Threads may be assigned to cores based on the number of cache misses processed by respective memory controllers. Methods may further include determining that a thread is latency-bound or bandwidth-bound. Threads may be assigned to cores based on the determination of the thread as latency-bound or bandwidth-bound. In response to the assignment of the threads to the cores, data for the thread may be stored in the assigned cores.

公开(公告)号：US09564202B2

公开(公告)日：2017-02-07

申请号：US14371180

申请日：2013-09-01

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Yan Solihin

IPC: G06F12/14 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/44 ,  G11C29/50 ,  G11C11/406 ,  G11C7/10 ,  G11C29/00 ,  G11C11/40

CPC classification number: G06F11/004 ,  G11C7/1072 ,  G11C11/40 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4074 ,  G11C29/023 ,  G11C29/028 ,  G11C29/44 ,  G11C29/50016 ,  G11C29/783 ,  G11C2211/4061

Abstract: Techniques described herein generally include methods and systems related to designing and operating a DRAM device that has significantly reduced refresh energy use. A method for designing a DRAM optimizes or otherwise improves the DRAM for energy efficiency based on a measured or predicted failure probability of memory cells in the DRAM. The DRAM may be configured to operate at an increased refresh interval, thereby reducing DRAM refresh energy but causing a predictable portion of the memory cells in the DRAM to leak electrical energy too quickly to retain data. The DRAM is further configured with a selected number of spare memory cells for replacing the “leaky” memory cells, so that operation of the DRAM at the increased refresh interval may result in little or no reduction in capacity of the DRAM.

Abstract translation: 本文描述的技术通常包括与设计和操作具有显着降低的刷新能量使用的DRAM设备相关的方法和系统。 基于DRAM中的存储器单元的测量或预测的故障概率，用于设计DRAM的方法优化或以其他方式改进用于能量效率的DRAM。 DRAM可以被配置为以增加的刷新间隔进行操作，从而减少DRAM刷新能量，但是使DRAM中的存储器单元的可预测部分太快地泄漏电能以保留数据。 DRAM还配置有用于替换“泄漏”存储单元的选定数量的备用存储器单元，使得在增加的刷新间隔的DRAM的操作可能导致DRAM的容量很少或不降低。

公开(公告)号：US09473426B2

公开(公告)日：2016-10-18

申请号：US14005520

申请日：2013-03-20

Applicant: Empire Technology Development LLC

Inventor： Yan Solihin

IPC: H04L12/66 ,  H04L12/931 ,  H04L12/947 ,  G06F12/08 ,  H04L12/933

CPC classification number: H04L49/60 ,  H04L45/60 ,  H04L49/101 ,  H04L49/251 ,  H04L49/252

Abstract: Technologies are generally described for methods and systems effective to implement hybrid routers in multicore architectures. A first tile may include a processor core, a cache configured to be in communication with the processor core and a router configured to be in communication with the cache. The router may be effective to move data with a packet switching channel or a circuit switching channel. The first tile may include switching logic configured to be in communication with the cache and the router. The switching logic may be effective to receive a routing objective that may relate to energy or delay costs in routing data through the network. The switching logic may select one of the packet switching channel or the circuit switching channel to move the data through the network based on the routing objective.

Abstract translation: 技术通常被描述为在多核架构中实现混合路由器有效的方法和系统。 第一瓦片可以包括处理器核心，被配置为与处理器核心通信的高速缓存器和配置成与高速缓存通信的路由器。 路由器可能有效地利用分组交换信道或电路交换信道来移动数据。 第一瓦片可以包括被配置为与高速缓存和路由器通信的交换逻辑。 切换逻辑可以有效地接收可能涉及通过网络路由数据的能量或延迟成本的路由目标。 切换逻辑可以选择分组交换信道或电路交换信道中的一个，以基于路由目的通过网络移动数据。

公开(公告)号：US08868800B2

公开(公告)日：2014-10-21

申请号：US13978655

申请日：2013-03-12

Applicant: Empire Technology Development, LLC

Inventor： Yan Solihin

IPC: G06F13/38 ,  G06F5/12 ,  G06F3/00

CPC classification number: G06F12/0842

Abstract: Technologies are generally described for methods and systems effective to provide accelerator buffer access. An operating system may allocate a range of addresses in virtual address spaces and a range of addresses in a buffer mapped region of a physical (or main) memory. A request to read from, or write to, data by an application may be read from, or written to, the virtual address space. A memory management unit may then map the read or write requests from the virtual address space to the main or physical memory. Multiple applications may be able to operate as if each application has exclusive access to the accelerator and its buffer. Multiple accesses to the buffer by application tasks may avoid a conflict because the memory controller may be configured to fetch data based on respective application identifiers assigned to the applications. Each application may be assigned a different application identifier.

Abstract translation: 通常描述有效提供加速器缓冲器访问的方法和系统的技术。 操作系统可以分配虚拟地址空间中的地址范围以及物理（或主）存储器的缓冲器映射区域中的地址范围。 从应用程序读取或写入数据的请求可以从虚拟地址空间读取或写入虚拟地址空间。 然后，存储器管理单元可以将来自虚拟地址空间的读取或写入请求映射到主存储器或物理存储器。 多个应用程序可能能够像每个应用程序具有对加速器及其缓冲区的独占访问一样操作。 通过应用任务对缓冲器的多次访问可以避免冲突，因为存储器控制器可以被配置为基于分配给应用的相应应用标识符来获取数据。 可以为每个应用分配不同的应用标识符。

公开(公告)号：US20140281058A1

公开(公告)日：2014-09-18

申请号：US13978655

申请日：2013-03-12

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT, LLC

Inventor： Yan Solihin

IPC: G06F5/12

CPC classification number: G06F12/0842

Abstract: Technologies are generally described for methods and systems effective to provide accelerator buffer access. An operating system may allocate a range of addresses in virtual address spaces and a range of addresses in a buffer mapped region of a physical (or main) memory. A request to read from, or write to, data by an application may be read from, or written to, the virtual address space. A memory management unit may then map the read or write requests from the virtual address space to the main or physical memory. Multiple applications may be able to operate as if each application has exclusive access to the accelerator and its buffer. Multiple accesses to the buffer by application tasks may avoid a conflict because the memory controller may be configured to fetch data based on respective application identifiers assigned to the applications. Each application may be assigned a different application identifier.

Abstract translation: 通常描述有效提供加速器缓冲器访问的方法和系统的技术。 操作系统可以分配虚拟地址空间中的地址范围以及物理（或主）存储器的缓冲器映射区域中的地址范围。 从应用程序读取或写入数据的请求可以从虚拟地址空间读取或写入虚拟地址空间。 然后，存储器管理单元可以将来自虚拟地址空间的读取或写入请求映射到主存储器或物理存储器。 多个应用程序可能能够像每个应用程序具有对加速器及其缓冲区的独占访问一样操作。 通过应用任务对缓冲器的多次访问可以避免冲突，因为存储器控制器可以被配置为基于分配给应用的相应应用标识符来获取数据。 可以为每个应用分配不同的应用标识符。

公开(公告)号：US10152410B2

公开(公告)日：2018-12-11

申请号：US14442093

申请日：2014-03-28

Applicant: Empire Technology Development LLC

Inventor： Yan Solihin

IPC: G06F12/08 ,  G06F12/02 ,  G06F12/0893 ,  G06F12/123 ,  G06F12/0875 ,  G06F12/126

Abstract: Technologies are generally described manage MRAM cache writes in processors. In some examples, when a write request is received with data to be stored in an MRAM cache, the data may be evaluated to determine whether the data is to be further processed. In response to a determination that the data is to be further processed, the data may be stored in a write cache associated with the MRAM cache. In response to a determination that the data is not to be further processed, the data may be stored in the MRAM cache.