公开(公告)号：US09099487B2

公开(公告)日：2015-08-04

申请号：US14098194

申请日：2013-12-05

申请人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L29/861 ,  H01L31/107 ,  H01L29/66 ,  H01L29/866

CPC分类号： H01L29/866 ,  H01L21/76224 ,  H01L29/0611 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/08 ,  H01L29/66106

摘要： Zener diode structures and related fabrication methods and semiconductor devices are provided. An exemplary semiconductor device includes first and second Zener diode structures. The first Zener diode structure includes a first region, a second region that is adjacent to the first region, and a third region adjacent to the first region and the second region to provide a junction that is configured to influence a first reverse breakdown voltage of a junction between the first region and the second region. The second Zener diode structure includes a fourth region, a fifth region that is adjacent to the fourth region, and a sixth region adjacent to the fourth region and the fifth region to provide a junction configured to influence a second reverse breakdown voltage of a junction between the fourth region and the fifth region, wherein the second reverse breakdown voltage and the first reverse breakdown voltage are different.

摘要翻译： 提供齐纳二极管结构及相关制造方法和半导体器件。 示例性半导体器件包括第一和第二齐纳二极管结构。 第一齐纳二极管结构包括第一区域，与第一区域相邻的第二区域，以及与第一区域和第二区域相邻的第三区域，以提供被配置为影响第一区域的第一反向击穿电压 第一区域和第二区域之间的连接处。 第二齐纳二极管结构包括第四区域，与第四区域相邻的第五区域以及与第四区域和第五区域相邻的第六区域，以提供被配置为影响第二区域的第二反向击穿电压 第四区域和第五区域，其中第二反向击穿电压和第一反向击穿电压不同。

公开(公告)号：US20140001594A1

公开(公告)日：2014-01-02

申请号：US13537299

申请日：2012-06-29

申请人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L29/872 ,  H01L21/329

CPC分类号： H01L29/872 ,  H01L29/0692 ,  H01L29/417 ,  H01L29/66143

摘要： A Schottky diode includes a device structure having a central portion and a plurality of fingers. Distal portions of the fingers overlie leakage current control (LCC) regions. An LCC region is relatively narrow and deep, terminating in proximity to a buried layer of like polarity. Under reverse bias, depletion regions forming in an active region lying between the buried layer and the LCC regions occupy the entire extent of the active region and thereby provide a carrier depleted wall. An analogous depletion region occurs in the active region residing between any pair of adjacent fingers. If the fingers include latitudinal oriented fingers and longitudinal oriented fingers, depletion region blockades in three different orthogonal orientations may occur. The formation of the LCC regions may include the use of a high dose, low energy phosphorous implant using an LCC implant mask and the isolation structures as an additional hard mask.

摘要翻译： 肖特基二极管包括具有中心部分和多个指状物的器件结构。 手指的远端覆盖泄漏电流控制（LCC）区域。 LCC区域相对较窄和深，终止于类似极性的掩埋层附近。 在反向偏压下，在位于掩埋层和LCC区域之间的有源区域中形成的耗尽区域占据有源区域的整个范围，从而提供载流子耗尽的壁。 类似的耗尽区发生在驻留在任何一对相邻手指之间的有源区域中。 如果手指包括纬向取向的指状物和纵向取向的指状物，则可能发生三个不同正交取向的耗尽区域封锁。 LCC区域的形成可以包括使用使用LCC植入物掩模的高剂量，低能量磷植入物，并且将隔离结构用作附加的硬掩模。

公开(公告)号：US20140061731A1

公开(公告)日：2014-03-06

申请号：US13605357

申请日：2012-09-06

申请人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L29/872 ,  H01L21/329

CPC分类号： H01L29/66893 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/08 ,  H01L29/1066 ,  H01L29/107 ,  H01L29/66143 ,  H01L29/872

摘要： A device includes a semiconductor substrate, first and second electrodes supported by the semiconductor substrate, laterally spaced from one another, and disposed at a surface of the semiconductor substrate to form an Ohmic contact and a Schottky junction, respectively. The device further includes a conduction path region in the semiconductor substrate, having a first conductivity type, and disposed along a conduction path between the first and second electrodes, a buried region in the semiconductor substrate having a second conductivity type and disposed below the conduction path region, and a device isolating region electrically coupled to the buried region, having the second conductivity type, and defining a lateral boundary of the device. The device isolating region is electrically coupled to the second electrode such that a voltage at the second electrode during operation is applied to the buried region to deplete the conduction path region.

摘要翻译： 一种器件包括半导体衬底，由半导体衬底支撑的第一和第二电极，彼此横向间隔开，并分别设置在半导体衬底的表面以形成欧姆接触和肖特基结。 该器件还包括半导体衬底中的导电通路区域，具有第一导电类型，并且沿第一和第二电极之间的导电路径设置，半导体衬底中的具有第二导电类型并设置在导电路径下方的掩埋区域 以及电耦合到所述掩埋区域的器件隔离区域，具有所述第二导电类型，并且限定所述器件的横向边界。 器件隔离区域电耦合到第二电极，使得在操作期间第二电极处的电压被施加到掩埋区域以耗尽导电路径区域。

公开(公告)号：US20140061715A1

公开(公告)日：2014-03-06

申请号：US13601831

申请日：2012-08-31

申请人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L29/68 ,  H01L21/329

CPC分类号： H01L29/866 ,  H01L29/0692

摘要： A disclosed Zener diode includes, in one embodiment, an anode region and a cathode region that form a shallow sub-surface latitudinal Zener junction. The Zener diode may further include an anode contact region interconnecting the anode region with a contact located away from the Zener junction region and a silicide blocking structure overlying the anode region. The Zener diode may also include one or more shallow, sub-surface longitudinal p-n junctions at the junctions between lateral edges of the cathode region and the adjacent region. The adjacent region may be a heavily doped region such as the anode contact region. In other embodiments, the Zener diode may include a breakdown voltage boost region comprising a more lightly doped region located between the cathode region and the anode contact region.

摘要翻译： 在一个实施例中，公开的齐纳二极管包括形成浅亚表面纬向齐纳结的阳极区域和阴极区域。 齐纳二极管还可以包括将阳极区域与位于远离齐纳结区域的触点和覆盖阳极区域的硅化物阻挡结构互连的阳极接触区域。 齐纳二极管还可以包括在阴极区域和相邻区域的侧边缘之间的接合处的一个或多个浅的子表面纵向p-n结。 相邻区域可以是诸如阳极接触区域的重掺杂区域。 在其他实施例中，齐纳二极管可以包括击穿电压升压区域，其包括位于阴极区域和阳极接触区域之间的较轻掺杂区域。

公开(公告)号：US09018673B2

公开(公告)日：2015-04-28

申请号：US13601831

申请日：2012-08-31

申请人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L29/66 ,  H01L29/866 ,  H01L29/06

CPC分类号： H01L29/866 ,  H01L29/0692

摘要： A disclosed Zener diode includes, in one embodiment, an anode region and a cathode region that form a shallow sub-surface latitudinal Zener junction. The Zener diode may further include an anode contact region interconnecting the anode region with a contact located away from the Zener junction region and a silicide blocking structure overlying the anode region. The Zener diode may also include one or more shallow, sub-surface longitudinal p-n junctions at the junctions between lateral edges of the cathode region and the adjacent region. The adjacent region may be a heavily doped region such as the anode contact region. In other embodiments, the Zener diode may include a breakdown voltage boost region comprising a more lightly doped region located between the cathode region and the anode contact region.

摘要翻译： 在一个实施例中，公开的齐纳二极管包括形成浅亚表面纬向齐纳结的阳极区域和阴极区域。 齐纳二极管还可以包括将阳极区域与位于远离齐纳结区域的触点和覆盖阳极区域的硅化物阻挡结构互连的阳极接触区域。 齐纳二极管还可以包括在阴极区域和相邻区域的侧边缘之间的接合处的一个或多个浅的子表面纵向p-n结。 相邻区域可以是诸如阳极接触区域的重掺杂区域。 在其他实施例中，齐纳二极管可以包括击穿电压升压区域，其包括位于阴极区域和阳极接触区域之间的较轻掺杂区域。

公开(公告)号：US20140242762A1

公开(公告)日：2014-08-28

申请号：US14269825

申请日：2014-05-05

申请人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L29/66 ,  H01L27/06

CPC分类号： H01L29/66893 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/08 ,  H01L29/1066 ,  H01L29/107 ,  H01L29/66143 ,  H01L29/872

摘要： A method of fabricating a Schottky diode having an integrated junction field-effect transistor (JFET) device includes forming a conduction path region in a semiconductor substrate along a conduction path of the Schottky diode. The conduction path region has a first conductivity type. A lateral boundary of an active area of the Schottky diode is defined by forming a well of a device isolating structure in the semiconductor substrate having a second conductivity type. An implant of dopant of the second conductivity type is conducted to form a buried JFET gate region in the semiconductor substrate under the conduction path region. The implant is configured to further form the device isolating structure in which the Schottky diode is disposed.

摘要翻译： 制造具有集成结型场效应晶体管（JFET）器件的肖特基二极管的方法包括沿着肖特基二极管的导通路径在半导体衬底中形成导电路径区域。 导电路径区域具有第一导电类型。 通过在具有第二导电类型的半导体衬底中形成器件隔离结构的阱来限定肖特基二极管的有源区的横向边界。 进行第二导电类型的掺杂剂的注入以在导电路径区域下的半导体衬底中形成掩埋JFET栅极区域。 植入物构造成进一步形成其中设置肖特基二极管的器件隔离结构。

公开(公告)号：US20090267127A1

公开(公告)日：2009-10-29

申请号：US12109736

申请日：2008-04-25

申请人： Weize Chen ,  Richard J. De Souza ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Richard J. De Souza ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L27/115 ,  H01L21/8247 ,  H01L21/8242

CPC分类号： H01L29/7881 ,  G11C16/10 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324

摘要： A single-poly non-volatile memory includes a PMOS select transistor (210) formed with a select gate (212), and P+ source and drain regions (211, 213) formed in a shared n-well region (240), a serially connected PMOS floating gate transistor (220) formed with part of a p-type floating gate layer (222) and P+ source and drain regions (221, 223) formed in the shared n-well region (240), and a coupling capacitor (230) formed over a p-well region (250) and connected to the PMOS floating gate transistor (220), where the coupling capacitor (230) includes a first capacitor plate formed with a second part of the p-type floating gate layer (222) and an underlying portion of the p-well region (250).

摘要翻译： 单多晶非易失性存储器包括形成有选择栅极（212）的PMOS选择晶体管（210），以及形成在共享的n阱区域（240）中的P +源区和漏区（211,213） 形成有形成在共用n阱区域（240）中的p型浮栅（222）和P +源区和漏区（221,223）的一部分的连接PMOS浮栅晶体管（220）和耦合电容器 230），其形成在p阱区（250）上并连接到PMOS浮栅晶体管（220），其中耦合电容器（230）包括形成有p型浮栅的第二部分的第一电容器板（ 222）和p阱区（250）的下层部分。

公开(公告)号：US09543379B2

公开(公告)日：2017-01-10

申请号：US14218330

申请日：2014-03-18

申请人： Hongning Yang ,  Xin Lin ,  Zhihong Zhang ,  Jiang-Kai Zuo

发明人： Hongning Yang ,  Xin Lin ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/36 ,  H01L21/8234 ,  H01L27/12

CPC分类号： H01L29/063 ,  H01L21/76283 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/1203 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1087 ,  H01L29/36 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7823 ,  H01L29/7824 ,  H01L29/7835

摘要： A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate and having a first conductivity type, a body region disposed in the semiconductor substrate, having a second conductivity type, and in which the source region is disposed, a drift region disposed in the semiconductor substrate, having the first conductivity type, and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions, a device isolation region disposed in the semiconductor substrate and laterally surrounding the body region and the drift region, and a breakdown protection region disposed between the device isolation region and the body region and having the first conductivity type.

摘要翻译： 一种器件包括半导体衬底，设置在半导体衬底中并具有第一导电类型的源极和漏极区域，设置在半导体衬底中的体区，具有第二导电类型，并且其中设置源极区，漂移区 设置在具有第一导电类型的半导体衬底中，并且在施加源极和漏极区域之间的偏置电压时，电荷载体在工作期间漂移，设置在半导体衬底中并横向围绕身体区域的器件隔离区域和 漂移区域和设置在器件隔离区域和体区之间并具有第一导电类型的击穿保护区域。

公开(公告)号：US20160025745A1

公开(公告)日：2016-01-28

申请号：US14814238

申请日：2015-07-30

申请人： Jia Guo ,  Xin Lin ,  Steve Georas ,  Patricia Sime

发明人： Jia Guo ,  Xin Lin ,  Steve Georas ,  Patricia Sime

IPC分类号： G01N33/68 ,  A61K38/44 ,  A61K31/713 ,  C12Q1/68

CPC分类号： G01N33/6875 ,  A61K31/7088 ,  A61K31/713 ,  A61K38/44 ,  A61K39/395 ,  A61K39/39533 ,  A61K39/39583 ,  A61K45/00 ,  C12Q1/6883 ,  C12Q2600/106 ,  C12Q2600/112 ,  C12Q2600/136 ,  C12Q2600/154 ,  C12Q2600/158 ,  C12Y114/11027 ,  G01N2800/10 ,  G01N2800/52

摘要： The present invention is directed to methods of diagnosing and treating a fibrotic condition in a mammalian subject. These methods involve measuring the levels of trimethylation at lysine residue 27 of histone-3 and/or measuring the expression levels of EZH2 or YY-1. Agents useful for treating fibrosis or a fibrotic condition are also disclosed.

摘要翻译： 本发明涉及在哺乳动物受试者中诊断和治疗纤维化病症的方法。 这些方法包括测量组蛋白-3的赖氨酸残基27处的三甲基化水平和/或测量EZH2或YY-1的表达水平。 还公开了可用于治疗纤维化或纤维化病症的药剂。

公开(公告)号：US20150380513A1

公开(公告)日：2015-12-31

申请号：US14844608

申请日：2015-09-03

申请人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kai Zuo

IPC分类号： H01L29/66 ,  H01L21/265 ,  H01L21/762 ,  H01L29/10 ,  H01L21/266 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/6625 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/08 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/735

摘要： A method of fabricating a bipolar transistor device includes performing a first plurality of implantation procedures to implant dopant of a first conductivity type to form emitter and collector regions laterally spaced from one another in a semiconductor substrate, and performing a second plurality of implantation procedures to implant dopant of a second conductivity type in the semiconductor substrate to form a composite base region. The composite base region includes a base contact region, a buried region through which a buried conduction path between the emitter and collector regions is formed during operation, and a base link region electrically connecting the base contact region and the buried region. The base link region has a dopant concentration level higher than the buried region and is disposed laterally between the emitter and collector regions.

摘要翻译： 一种制造双极晶体管器件的方法包括：执行第一多个注入步骤以注入第一导电类型的掺杂剂，以形成在半导体衬底中彼此横向隔开的发射极和集电极区，以及执行第二多个植入步骤以植入 半导体衬底中的第二导电类型的掺杂剂以形成复合基极区域。 复合基极区域包括基极接触区域，在工作期间形成发射极和集电极区域之间的掩埋传导路径的掩埋区域和电连接基极接触区域和掩埋区域的基极连接区域。 基极区域的掺杂剂浓度水平高于掩埋区域，并且横向设置在发射极和集电极区域之间。