公开(公告)号：US5295090A

公开(公告)日：1994-03-15

申请号：US66674

申请日：1993-05-24

申请人： Hung-Cheng Hsieh ,  William S. Carter ,  Charles S. Erickson ,  Edmond Y. Cheung

发明人： Hung-Cheng Hsieh ,  William S. Carter ,  Charles S. Erickson ,  Edmond Y. Cheung

IPC分类号： G06F7/50 ,  G06F7/506

CPC分类号： G06F7/506

摘要： Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal.

摘要翻译： 使用包括组合函数发生器和存储元件的多个块并且通过可编程互连结构互连的可编程逻辑器件，用于执行使用用于产生进位功能的逻辑的算术功能。 当要处理大量的位时，进位功能通常会导致显着的延迟或需要大量附加组件以高速获得结果。 本发明提供逻辑块内的专用硬件，用于快速执行进位功能并具有最少数量的部件。 本发明利用以下事实：当要添加的两个二进制比特不相等时，要添加到两个比特的进位信号可以被传播到下一个更高有效比特，并且该比特中的一个可以用作进位信号，当 这些位是相等的。

公开(公告)号：US4642487A

公开(公告)日：1987-02-10

申请号：US655007

申请日：1984-09-26

申请人： William S. Carter

发明人： William S. Carter

IPC分类号： H01L21/82 ,  H01L27/118 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177 ,  H03K19/20 ,  H03K17/693

CPC分类号： H03K19/17704

摘要： A special interconnect circuit which connects adjacent configurable logic elements (CLEs) in a configurable logic array (CLA) without using the general interconnect structure of the CLA. In one embodiment, an array of CLEs is arranged in rows and columns and a special vertical lead circuit is provided which connects an output lead of a given CLE in a given column to a selected input lead of the CLE above it and below in the same column. Special horizontal lead circuits are provided which connect a given output lead of a given CLE to a selected adjacent input lead of the CLE in the same row.

摘要翻译： 在可配置逻辑阵列（CLA）中连接相邻可配置逻辑元件（CLE）而不使用CLA的一般互连结构的特殊互连电路。 在一个实施例中，CLE阵列被布置成行和列，并且提供特殊的垂直引线电路，其将给定列中的给定CLE的输出引线连接到相同的CLE上方的CLE的选定输入引线 柱。 提供了特定的水平引线电路，其将给定CLE的给定输出引线连接到同一行中CLE的选定的相邻输入引线。

公开(公告)号：US20130159847A1

公开(公告)日：2013-06-20

申请号：US13325183

申请日：2011-12-14

申请人： Christine A. Banke ,  William S. Carter ,  Pawan Khera ,  James R. Kraemer ,  Elizabeth V. Woodward

发明人： Christine A. Banke ,  William S. Carter ,  Pawan Khera ,  James R. Kraemer ,  Elizabeth V. Woodward

IPC分类号： G06F17/21 ,  G06F15/16

CPC分类号： G06F17/2735

摘要： A mechanism is provided for utilizing a dynamic personal dictionary in enhanced collaboration. A comparison is performed for each portion of entered text of the electronic communication with text identified in the dynamic personal dictionary. Responsive to a portion of the entered text matching an entry in the dynamic personal dictionary, the portion of the entered text is marked with an identifier, the identifier indicating that the portion of the entered text has an associated context definition. The electronic communication is then sent to a set of client devices with a set of marked text portions and associated identifiers.

摘要翻译： 提供了一种用于在增强协作中利用动态个人字典的机制。 对动态个人字典中识别的文本进行电子通信输入文本的每一部分的比较。 响应于输入的文本的一部分匹配动态个人字典中的条目，输入的文本的部分用标识符标记，该标识符指示输入的文本的部分具有关联的上下文定义。 然后，电子通信被发送到具有一组标记的文本部分和相关联的标识符的一组客户端设备。

公开(公告)号：US20130158978A1

公开(公告)日：2013-06-20

申请号：US13325202

申请日：2011-12-14

申请人： Christine A. Banke ,  William S. Carter ,  Pawan Khera ,  James R. Kraemer ,  Elizabeth V. Woodward

发明人： Christine A. Banke ,  William S. Carter ,  Pawan Khera ,  James R. Kraemer ,  Elizabeth V. Woodward

IPC分类号： G06F17/27

CPC分类号： G06F17/27

摘要： A mechanism is provided for adapting vocabulary levels in a collaborative session. A vocabulary level indicator is received for a first user in the collaborative session. During generation of an electronic communication by a second user in the collaborative session, text entered in the electronic communication is scanned in order to identify a vocabulary level associated with text. The vocabulary level associated with the text is compared to the vocabulary level indicator for the first user. Responsive to the text exceeding the vocabulary level indicator for the first user thereby indicating violating text, an indication is provided to the second user that the violating text is above a vocabulary level of the first user.

摘要翻译： 提供了一种用于在协作会话中调整词汇级别的机制。 在协作会话中为第一用户接收到词汇级指示符。 在协作会话期间由第二用户进行电子通信的生成期间，扫描输入到电子通信中的文本，以便识别与文本相关联的词汇级别。 将与文本相关联的词汇级别与第一用户的词汇级指标进行比较。 响应于超过第一用户的词汇级指示符的文本，从而指示违反文本，向第二用户提供了违反文本高于第一用户的词汇级别的指示。

公开(公告)号：US4758985A

公开(公告)日：1988-07-19

申请号：US845287

申请日：1986-03-28

申请人： William S. Carter

发明人： William S. Carter

IPC分类号： G11C19/28 ,  H03K3/037 ,  H03K5/1534 ,  H03K19/173 ,  G11C13/00

CPC分类号： G11C19/282 ,  H03K19/1733 ,  H03K19/1736 ,  H03K3/037 ,  H03K5/1534

摘要： A microprocessor controlled configurable logic circuit achieves versatility by including a configurable combinational logic element, a configurable storage circuit, a configurable status buffer, and a configurable output select logic. The input signals to the configurable combinational logic element are input signals to the configurable logic circuit and feedback signals from the storage circuit. The storage circuit may be configured to operate as a D flip-flop with or without set and reset inputs, or as an edge detector. In conjunction with the combinational logic element, the storage circuit may also operate as a stage of a shift register or counter. The output select logic selects output from among the output signals of the combinational logic element and the storage circuit. The configurable status buffer may be configured to provide status information on selected important internal signals of the configurable logic circuit. A microprocessor interface structure may access an array of these configurable logic circuits through the status buffer to read different internal output signals from different circuits in the array. Providing separate input and output to a microprocessor leaves the storage element free for other uses and does not require the logic provided by the logic elements.

摘要翻译： 微处理器控制的可配置逻辑电路通过包括可配置组合逻辑元件，可配置存储电路，可配置状态缓冲器和可配置输出选择逻辑来实现多功能性。 到可配置组合逻辑元件的输入信号是到可配置逻辑电路的输入信号和来自存储电路的反馈信号。 存储电路可以被配置为作为具有或不具有设置和复位输入的D触发器或作为边缘检测器来操作。 结合组合逻辑元件，存储电路也可以作为移位寄存器或计数器的级进行操作。 输出选择逻辑从组合逻辑元件和存储电路的输出信号中选择输出。 可配置状态缓冲器可以被配置为提供关于可配置逻辑电路的选择的重要内部信号的状态信息。 微处理器接口结构可以通过状态缓冲器访问这些可配置逻辑电路的阵列，以从阵列中的不同电路读取不同的内部输出信号。 向微处理器提供单独的输入和输出使存储元件免于其他用途，并且不需要由逻辑元件提供的逻辑。

公开(公告)号：US4695740A

公开(公告)日：1987-09-22

申请号：US655008

申请日：1984-09-26

申请人： William S. Carter

发明人： William S. Carter

IPC分类号： H03F3/62 ,  H03K5/02 ,  H03K17/687 ,  H03K17/56 ,  H04B3/38

CPC分类号： H03K5/026

摘要： Bidirectional amplifier employs a single buffer amplifier (64). The bidirectional amplifier is programmed by applying a control signal (Q) and its complementary signal (Q), which establishes the state of four pass transistors (P'.sub.1, P'.sub.2, P'.sub.3, P'.sub.4) or four CMOS transmission gates (T.sub.1, T.sub.2, T.sub.3, T.sub.4). For a first selection of the control signal, the bidirectional amplifier receives an input signal on a first lead (A') and produces an amplified signal on a second lead (B'). For a second selection of the control signal, the amplifier receives an input signal on the second lead (B') and produces an amplified output signal on the first lead (A').

摘要翻译： 双向放大器采用单缓冲放大器（64）。 通过施加控制信号（Q）及其互补信号（＆upbar＆Q）来编程双向放大器，其建立四通晶体管（P'1，P'2，P'3，P'4）或四个CMOS的状态 传输门（T1，T2，T3，T4）。 对于控制信号的第一选择，双向放大器在第一引线（A'）上接收输入信号，并在第二引线（B'）上产生放大信号。 对于控制信号的第二选择，放大器在第二引线（B'）上接收输入信号，并在第一引线（A'）上产生放大的输出信号。

公开(公告)号：US4234366A

公开(公告)日：1980-11-18

申请号：US940791

申请日：1978-09-01

申请人： Douglas M. Brewer ,  Alan Mawson ,  William S. Carter

发明人： Douglas M. Brewer ,  Alan Mawson ,  William S. Carter

IPC分类号： B32B5/18 ,  B29B11/00 ,  B29B17/00 ,  B29B17/04 ,  D06N3/06 ,  D06N7/00 ,  E04F15/16 ,  B29H19/00 ,  B32B5/20 ,  B32B25/08

CPC分类号： D06N3/06 ,  Y10T428/23979 ,  Y10T428/24504 ,  Y10T428/24876 ,  Y10T428/24901 ,  Y10T428/249986 ,  Y10T428/252

摘要： Floor or wall covering is provided and comprises a decorative opaque surface layer bonded to a sheet backing obtained by comminuting, softening and resheeting a sheet material comprising a fibrous reinforcement, a layer of foamed vinyl resin and pigmented decoration. The fibrous reinforcement is normally of glass fibres and particulate inorganic filler is incorporated into the mass that is resheeted.

摘要翻译： 提供了地板或墙壁覆盖物，并且包括结合到通过粉碎，软化和重新包覆纤维增强材料，发泡乙烯基树脂层和着色装饰的片材而获得的片材背衬的装饰性不透明表面层。 纤维增强材料通常为玻璃纤维，颗粒状无机填料被并入被重新分层的团块中。

公开(公告)号：US08738364B2

公开(公告)日：2014-05-27

申请号：US13325202

申请日：2011-12-14

申请人： Christine A. Banke ,  William S. Carter ,  Pawan Khera ,  James R. Kraemer ,  Elizabeth V. Woodward

发明人： Christine A. Banke ,  William S. Carter ,  Pawan Khera ,  James R. Kraemer ,  Elizabeth V. Woodward

IPC分类号： G06F17/27 ,  G10L21/00 ,  G10L25/00

CPC分类号： G06F17/27

摘要： A mechanism is provided for adapting vocabulary levels in a collaborative session. A vocabulary level indicator is received for a first user in the collaborative session. During generation of an electronic communication by a second user in the collaborative session, text entered in the electronic communication is scanned in order to identify a vocabulary level associated with text. The vocabulary level associated with the text is compared to the vocabulary level indicator for the first user. Responsive to the text exceeding the vocabulary level indicator for the first user thereby indicating violating text, an indication is provided to the second user that the violating text is above a vocabulary level of the first user.

摘要翻译： 提供了一种用于在协作会话中调整词汇级别的机制。 在协作会话中为第一用户接收到词汇级指示符。 在协作会话期间由第二用户进行电子通信的生成期间，扫描输入到电子通信中的文本，以便识别与文本相关联的词汇级别。 将与文本相关联的词汇级别与第一用户的词汇级指标进行比较。 响应于超过第一用户的词汇级指示符的文本，从而指示违反文本，向第二用户提供了违反文本高于第一用户的词汇级别的指示。

公开(公告)号：US06748368B1

公开(公告)日：2004-06-08

申请号：US09477650

申请日：2000-01-05

申请人： Stephen M. Trimberger ,  William S. Carter

发明人： Stephen M. Trimberger ,  William S. Carter

IPC分类号： H03K19177

CPC分类号： G06F21/76 ,  G06F17/5054 ,  G06Q99/00 ,  H03K19/17732 ,  H03K19/1776 ,  H03K19/17768

摘要： A programmable logic device includes a non-volatile permission memory block to enable a customer to utilize a proprietary core. In one embodiment, the core supplier designs its core to check for a specified permission bit or bit pattern in the permission memory block before the core will operate. If the permission bit or bit pattern is set properly, the core functions correctly when implemented in the PLD. If not, the core will not function. To prevent the customer from modifying the core such that it no longer depends upon the permission bits to function, the configuration bitstream used to program the PLD can be encrypted before and during transmission to the PLD. This encryption ensures security of the customer's logic design as well as the supplier's core design. In this manner, the customer remains dependent upon properly set permission memory bits, i.e. proper authorization, to obtain core functionality.

摘要翻译： 可编程逻辑器件包括非易失性许可存储器块，以使客户能够利用专有的核心。 在一个实施例中，核心供应商设计其核心以在核心将运行之前在许可存储器块中检查指定的许可位或位模式。 如果权限位或位模式正确设置，则在PLD中实现时，内核正常工作。 如果没有，核心将不起作用。 为了防止客户修改核心，使得它不再依赖于许可位的功能，用于编程PLD的配置比特流可以在传输到PLD之前和期间被加密。 这种加密确保了客户逻辑设计的安全性以及供应商的核心设计。 以这种方式，客户保持依赖于正确设置的权限存储位，即适当授权来获得核心功能。

公开(公告)号：US5140193A

公开(公告)日：1992-08-18

申请号：US499759

申请日：1990-03-27

申请人： Ross H. Freeman, deceased ,  Khue Duong ,  Hung-Cheng Hsieh ,  Charles R. Erickson ,  William S. Carter

发明人： Ross H. Freeman, deceased ,  Khue Duong ,  Hung-Cheng Hsieh ,  Charles R. Erickson ,  William S. Carter

IPC分类号： G06F3/00 ,  H01L21/82 ,  H03K19/173

CPC分类号： H03K19/1736

摘要： A structure especially useful in a configurable logic array includes a plurality of conductive interconnect lines located along the perimeter of a logic array chip. Lines running from exterior pins or pads can be used by a programmable interconnect circuit to control signals applied to these interconnect lines. In particular, both the signal and the complement of the signal can be used by the programmable interconnect to control application of a supply voltage to an interconnect line. A second supply voltage is applied through a resistor to the interconnect line with the result that the interconnect line will carry a logical signal representing a logical function, for example AND, of a selected set of input signals or their complements. Lines running from points interior to the configurable logic array chip may also contribute to the signal generated on an interconnect line. In one embodiment, bidirectional programmable interconnect circuits allow the input pins to function as either input or output pins. An application of the decoder circuit is described for use with a latch as a data/address demultiplexer.