利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

65 条记录 (耗时 0.025 秒)

    Drift cancellation technique for use in clock-forwarding architectures
    11.
    发明授权
    Drift cancellation technique for use in clock-forwarding architectures 有权
    用于时钟转发架构的漂移消除技术

    公开(公告)号：US07724852B2

    公开(公告)日：2010-05-25

    申请号：US11468517

    申请日：2006-08-30

    申请人： Kun-Yung Chang ,  Fariborz Assaderaghi

    发明人： Kun-Yung Chang ,  Fariborz Assaderaghi

    IPC分类号： H04L1/02

    CPC分类号： H03L7/00 ,  H03L7/06

    摘要： A circuit includes a frequency synthesizer, N phase mixers coupled to the frequency synthesizer, a plurality of receivers, and a calibration circuit. The frequency synthesizer is to receive a reference clock signal and is to output a primary clock signal. A respective phase mixer in the N phase mixers is to output a respective secondary clock signal having a corresponding phase. A respective receiver in the plurality of receivers is coupled to two of the N phase mixers, and at a respective time is to receive data in accordance with the respective secondary clock signal from one of the two phase mixers coupled to the respective receiver. The calibration circuit is to calibrate a secondary clock signal output by a respective phase mixer in the N phase mixers by adjusting the phase of the secondary clock signal of the respective phase mixer.

    摘要翻译： 电路包括频率合成器，耦合到频率合成器的N相混频器，多个接收器和校准电路。 频率合成器是接收参考时钟信号，并输出主时钟信号。 N相混频器中的相应的混频器将输出具有相应相位的相应次级时钟信号。 多个接收机中的相应接收机耦合到N相混合器中的两个，并且在相应的时间是根据耦合到相应接收机的两个相位混合器之一的相应辅助时钟信号接收数据。 校准电路是通过调整相位相位混合器的次级时钟信号的相位来校准由N相混频器中的各个相位混频器输出的次级时钟信号。

    Drift Cancellation Technique for Use in Clock-Forwarding Architectures
    12.
    发明申请
    Drift Cancellation Technique for Use in Clock-Forwarding Architectures 有权
    用于时钟转发架构的漂移取消技术

    公开(公告)号：US20080056415A1

    公开(公告)日：2008-03-06

    申请号：US11468517

    申请日：2006-08-30

    申请人： Kun-Yung Chang ,  Fariborz Assaderaghi

    发明人： Kun-Yung Chang ,  Fariborz Assaderaghi

    IPC分类号： H04B1/10

    CPC分类号： H03L7/00 ,  H03L7/06

    摘要： A circuit includes a frequency synthesizer, N phase mixers coupled to the frequency synthesizer, a plurality of receivers, and a calibration circuit. The frequency synthesizer is to receive a reference clock signal and is to output a primary clock signal. A respective phase mixer in the N phase mixers is to output a respective secondary clock signal having a corresponding phase. A respective receiver in the plurality of receivers is coupled to two of the N phase mixers, and at a respective time is to receive data in accordance with the respective secondary clock signal from one of the two phase mixers coupled to the respective receiver. The calibration circuit is to calibrate a secondary clock signal output by a respective phase mixer in the N phase mixers by adjusting the phase of the secondary clock signal of the respective phase mixer.

    摘要翻译： 电路包括频率合成器，耦合到频率合成器的N相混频器，多个接收器和校准电路。 频率合成器是接收参考时钟信号，并输出主时钟信号。 N相混频器中的相应的混频器将输出具有相应相位的相应次级时钟信号。 多个接收机中的相应接收机耦合到N相混合器中的两个，并且在相应的时间是根据耦合到相应接收机的两个相位混合器之一的相应辅助时钟信号接收数据。 校准电路是通过调整相位相位混合器的次级时钟信号的相位来校准由N相混频器中的各个相位混频器输出的次级时钟信号。

    MOS transistors with raised sources and drains
    14.
    发明授权
    MOS transistors with raised sources and drains 失效
    MOS晶体管具有升高的源极和漏极

    公开(公告)号：US06429084B1

    公开(公告)日：2002-08-06

    申请号：US09885828

    申请日：2001-06-20

    申请人： Heemyong Park ,  Fariborz Assaderaghi ,  Dominic J. Schepis

    发明人： Heemyong Park ,  Fariborz Assaderaghi ,  Dominic J. Schepis

    IPC分类号： H01L21336

    CPC分类号： H01L29/66492 ,  H01L29/41783 ,  H01L29/458 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78621

    摘要： In raised source/drain CMOS processing, the prior art problem of lateral epi growth on the gate stack interfering physically with the raised S/D structures and producing device characteristics that vary along the length of the gate and the problem of overetch of the STI oxide during the preclean step is solved by using a sacrificial nitride layer to block both the STI region and the gate stack, together with a process sequence in which the halo and extension implants are performed after the S/D implant anneal.

    摘要翻译： 在升高的源极/漏极CMOS处理中，现有技术的栅极堆叠上的外延生长问题在物理上与升高的S / D结构物质干扰并产生沿栅极长度变化的器件特性以及STI氧化物的过蚀刻问题 在预清洗步骤期间，通过使用牺牲氮化物层来阻止STI区域和栅极堆叠，以及在S / D注入退火之后执行卤素和延伸注入的工艺顺序来解决。

    PHASE LINEARITY TEST CIRCUIT
    19.
    发明申请
    PHASE LINEARITY TEST CIRCUIT 有权
    相位线性测试电路

    公开(公告)号：US20070252735A1

    公开(公告)日：2007-11-01

    申请号：US11414751

    申请日：2006-04-28

    申请人： Xudong Shi ,  Fariborz Assaderaghi

    发明人： Xudong Shi ,  Fariborz Assaderaghi

    IPC分类号： H03M1/06

    CPC分类号： G01R31/31727

    摘要： A circuit includes a phase interpolator and a self test circuit. The phase interpolator is to provide a interpolator output having a phase corresponding to a respective phase step in a plurality of phase steps. The interpolator output is a weighted combination of one or more of a plurality of phasor signals. The self test circuit includes a phase detector coupled to a reference signal and the interpolator output, a phase-difference-to-voltage converter coupled to the phase detector, an analog-to-digital converter (ADC) coupled to the phase-difference-to-voltage converter, and control logic. The phase detector is to generate an output that is proportional to a phase difference between the reference signal and the interpolator output. The phase-difference-to-voltage converter is to convert the output from the phase detector into a corresponding voltage. The ADC is to convert an output from the phase-difference-to-voltage converter into a corresponding digital value. The control logic is to test the phase interpolator using the self-test circuit.

    摘要翻译： 电路包括相位内插器和自检电路。 相位插值器是提供具有对应于多个相位步骤中的相位相位阶段的相位的内插器输出。 内插器输出是多个相量信号中的一个或多个的加权组合。 自检电路包括耦合到参考信号和内插器输出的相位检测器，耦合到相位检测器的相位差电压转换器，耦合到相位差转换器的模 - 数转换器（ADC） 电压转换器和控制逻辑。 相位检测器将产生与参考信号和内插器输出之间的相位差成比例的输出。 相位差电压转换器将相位检测器的输出转换成相应的电压。 ADC将将相位差电压转换器的输出转换为相应的数字值。 控制逻辑是使用自检电路测试相位插值器。