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公开(公告)号：US20080128675A1
公开(公告)日：2008-06-05
申请号：US11606800
申请日：2006-11-30
IPC分类号： H01L45/00
CPC分类号： H01L45/1691 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： A phase change memory includes a cup-shaped heater element formed above a body. A tapered phase change region is formed on the cup-shaped heater element. The cup-shaped heater element is formed by depositing a stop layer of a first dielectric material over the body. A first sacrificial layer is deposited over the stop layer, the first sacrificial layer being of a second dielectric material that can be etched selectively with respect to the first dielectric material. An opening is etched in the first sacrificial layer and the stop layer. A heating layer is formed in the opening. The opening is filled with a filling material to obtain a structure having a cup-shaped heating region formed in the stop layer and excess portions extending over said stop layer. The excess portions by an etch selective with respect to the first dielectric material are removed.
摘要翻译： 相变存储器包括形成在主体上方的杯形加热器元件。 在杯形加热器元件上形成锥形相变区域。 杯状加热器元件通过在主体上沉积第一电介质材料的停止层而形成。 第一牺牲层沉积在停止层上，第一牺牲层是可相对于第一介电材料选择性地蚀刻的第二电介质材料。 在第一牺牲层和停止层中蚀刻开口。 在开口中形成加热层。 开口填充有填充材料，以获得形成在止挡层中的杯形加热区域和在所述停止层上延伸的多余部分的结构。 除去相对于第一介电材料选择性的蚀刻的多余部分。
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公开(公告)号：US08084789B2
公开(公告)日：2011-12-27
申请号：US12700440
申请日：2010-02-04
申请人： Fabio Pellizzer , Agostino Pirovano
发明人： Fabio Pellizzer , Agostino Pirovano
IPC分类号： H01L29/76
CPC分类号： H01L45/06 , H01L27/2427 , H01L27/2463 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/1675
摘要： A phase change memory includes a memory element and a selection element. The memory element is embedded in a dielectric and includes a resistive element having at least one sublithographic dimension and a storage region in contact with the resistive element. The selection element includes a chalcogenic material embedded in a dielectric. The chalcogenic material and the storage region are part of a stack having a common etched edge.
摘要翻译： 相变存储器包括存储元件和选择元件。 存储元件嵌入在电介质中，并且包括具有至少一个亚光刻尺寸的电阻元件和与电阻元件接触的存储区域。 选择元件包括埋在电介质中的硫属材料。 硫属材料和存储区域是具有共同蚀刻边缘的堆叠的一部分。
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公开(公告)号：US07898848B2
公开(公告)日：2011-03-01
申请号：US11788909
申请日：2007-04-23
申请人： Agostino Pirovano , Fabio Pellizzer
发明人： Agostino Pirovano , Fabio Pellizzer
IPC分类号： G11C11/00
CPC分类号： H01L29/735 , G11C13/0004 , G11C13/003 , G11C2213/76 , G11C2213/79 , H01L27/0207 , H01L27/1022 , H01L27/24
摘要： An array is formed by a plurality of cells, wherein each cell is formed by a bipolar junction selection transistor having a first, a second, and a control region. The cell includes a common region, forming the second regions of the selection transistors, and a plurality of shared control regions overlying the common region. Each shared control region forms the control regions of a plurality of adjacent selection transistors and accommodates the first regions of the plurality of adjacent selection transistors as well as contact portions of the shared control region. Blocks of adjacent selection transistors of the plurality of selection transistors share a contact portion and the first regions of a block of adjacent selection transistors are arranged along the shared control region between two contact portions. A plurality of biasing structures are formed between pairs of first regions of adjacent selection transistors, for modifying a charge distribution in the shared control region below the biasing structures.
摘要翻译： 阵列由多个单元形成，其中每个单元由具有第一，第二和控制区域的双极结选择晶体管形成。 单元包括形成选择晶体管的第二区域的公共区域和覆盖在公共区域上的多个共享控制区域。 每个共享控制区域形成多个相邻选择晶体管的控制区域并且容纳多个相邻选择晶体管的第一区域以及共享控制区域的接触部分。 多个选择晶体管的相邻选择晶体管的块共享接触部分，并且沿着两个接触部分之间的共享控制区域布置相邻选择晶体管的块的第一区域。 在相邻选择晶体管的第一区域对之间形成多个偏置结构，用于修改偏置结构下方的共享控制区域中的电荷分布。
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公开(公告)号：US07515460B2
公开(公告)日：2009-04-07
申请号：US11606762
申请日：2006-11-30
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , G11C2213/79
摘要： A method for programming a phase change memory cell is discussed. A phase change memory cell includes a memory element of a phase change material having a first state, in which the phase change material is crystalline and has a minimum resistance level, a second state in which the phase change material is amorphous and has a maximum resistance level, and a plurality of intermediate states, in which the phase change material includes both crystalline regions and amorphous regions and has intermediate resistance levels. According to the method, a plurality of programming pulses are provided to the phase change memory cell; programming energies respectively associated to the programming pulses are lower than a threshold energy which is required to bring the phase change material to the second state.
摘要翻译： 讨论了一种编程相变存储单元的方法。 相变存储单元包括具有第一状态的相变材料的存储元件，其中所述相变材料是晶体并且具有最小电阻水平，所述相变材料是非晶态且具有最大电阻的第二状态 电平和多个中间状态，其中相变材料包括结晶区域和非晶区域并具有中等电阻水平。 根据该方法，向相变存储单元提供多个编程脉冲; 分别与编程脉冲相关联的编程能量低于使相变材料进入第二状态所需的阈值能量。
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公开(公告)号：US20080259677A1
公开(公告)日：2008-10-23
申请号：US11788909
申请日：2007-04-23
申请人： Agostino Pirovano , Fabio Pellizzer
发明人： Agostino Pirovano , Fabio Pellizzer
IPC分类号： G11C11/00 , H01L21/331
CPC分类号： H01L29/735 , G11C13/0004 , G11C13/003 , G11C2213/76 , G11C2213/79 , H01L27/0207 , H01L27/1022 , H01L27/24
摘要： An array is formed by a plurality of cells, wherein each cell is formed by a bipolar junction selection transistor having a first, a second, and a control region. The cell includes a common region, forming the second regions of the selection transistors, and a plurality of shared control regions overlying the common region. Each shared control region forms the control regions of a plurality of adjacent selection transistors and accommodates the first regions of the plurality of adjacent selection transistors as well as contact portions of the shared control region. Blocks of adjacent selection transistors of the plurality of selection transistors share a contact portion and the first regions of a block of adjacent selection transistors are arranged along the shared control region between two contact portions. A plurality of biasing structures are formed between pairs of first regions of adjacent selection transistors, for modifying a charge distribution in the shared control region below the biasing structures.
摘要翻译： 阵列由多个单元形成，其中每个单元由具有第一，第二和控制区域的双极结选择晶体管形成。 单元包括形成选择晶体管的第二区域的公共区域和覆盖在公共区域上的多个共享控制区域。 每个共享控制区域形成多个相邻选择晶体管的控制区域并且容纳多个相邻选择晶体管的第一区域以及共享控制区域的接触部分。 多个选择晶体管的相邻选择晶体管的块共享接触部分，并且沿着两个接触部分之间的共享控制区域布置相邻选择晶体管的块的第一区域。 在相邻选择晶体管的第一区域对之间形成多个偏置结构，用于修改偏置结构下方的共享控制区域中的电荷分布。
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公开(公告)号：US20070077699A1
公开(公告)日：2007-04-05
申请号：US11606762
申请日：2006-11-30
IPC分类号： H01L21/8238
CPC分类号： G11C13/0064 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , G11C2213/79
摘要： A method for programming a phase change memory cell is disclosed. A phase change memory cell includes a memory element of a phase change material having a first state, in which the phase change material is crystalline and has a minimum resistance level, a second state in which the phase change material is amorphous and has a maximum resistance level, and a plurality of intermediate states, in which the phase change material includes both crystalline regions and amorphous regions and has intermediate resistance levels. According to the method, a plurality of programming pulses are provided to the phase change memory cell; programming energies respectively associated to the programming pulses are lower than a threshold energy which is required to bring the phase change material to the second state.
摘要翻译： 公开了一种用于编程相变存储器单元的方法。 相变存储单元包括具有第一状态的相变材料的存储元件，其中所述相变材料是晶体并且具有最小电阻水平，所述相变材料是非晶态且具有最大电阻的第二状态 电平和多个中间状态，其中相变材料包括结晶区域和非晶区域并具有中等电阻水平。 根据该方法，向相变存储单元提供多个编程脉冲; 分别与编程脉冲相关联的编程能量低于使相变材料进入第二状态所需的阈值能量。
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17.发明申请Vertical MOSFET transistor, in particular operating as a selector in nonvolatile memory devices 有权垂直MOSFET晶体管，特别是用作非易失性存储器件中的选择器公开(公告)号：US20060278921A1
公开(公告)日：2006-12-14
申请号：US11411982
申请日：2006-04-26
申请人： Fabio Pellizzer , Agostino Pirovano
发明人： Fabio Pellizzer , Agostino Pirovano
IPC分类号： H01L29/76
CPC分类号： H01L29/7827 , G11C13/0004 , H01L27/2454 , H01L29/42392 , H01L29/665 , H01L29/66666 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： A vertical MOSFET transistor is formed in a body of semiconductor material having a surface. The transistor includes a buried conductive region of a first conductivity type; a channel region of a second conductivity type, arranged on top of the buried conductive region; a surface conductive region of the first conductivity type, arranged on top of the channel region and the buried conductive region; a gate insulation region, extending at the sides of and contiguous to the channel region; and a gate region extending at the sides of and contiguous to the gate insulation region.
摘要翻译： 在具有表面的半导体材料的主体中形成垂直MOSFET晶体管。 晶体管包括第一导电类型的掩埋导电区域; 布置在所述掩埋导电区域的顶部上的第二导电类型的沟道区域; 第一导电类型的表面导电区域布置在沟道区域和掩埋导电区域的顶部上; 栅极绝缘区域，在沟道区域的两侧延伸; 以及在栅极绝缘区域的侧面延伸并且与栅极绝缘区域邻接的栅极区域。
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公开(公告)号：US08243497B1
公开(公告)日：2012-08-14
申请号：US12628153
申请日：2009-11-30
申请人： Fabio Pellizzer , Agostino Pirovano , Augusto Benvenuti , Daniele Vimercati , Andrea Redaelli , Gerald Barkley
发明人： Fabio Pellizzer , Agostino Pirovano , Augusto Benvenuti , Daniele Vimercati , Andrea Redaelli , Gerald Barkley
IPC分类号： G11C11/00
CPC分类号： G11C8/14 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0033 , G11C13/0038 , G11C13/0069 , G11C2013/0071 , G11C2013/008 , G11C2213/79
摘要： A Phase Change Memory device with reduced programming disturbance and its operation are described. The Phase Change Memory includes an array with word lines and bit lines and voltage controlling elements coupled to bit lines adjacent to an addressed bit line to maintain the voltage of the adjacent bit lines within an allowed range.
摘要翻译： 描述了具有减少的编程干扰及其操作的相变存储器件。 相变存储器包括具有字线和位线的阵列，以及耦合到与寻址位线相邻的位线的电压控制元件，以将相邻位线的电压维持在允许的范围内。
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19.发明申请公开(公告)号：US20110039391A1
公开(公告)日：2011-02-17
申请号：US12912829
申请日：2010-10-27
IPC分类号： H01L21/331
摘要： A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed in a first direction down to the base and in a second direction down to the collector. The trenches may be used to form local enhancement implants into the exposed portion of the base and collector in each trench. As a result of the local enhancement implants, in some embodiments, leakage current may be reduced, active current capability may be higher, gain may be higher, base resistance may be reduced, breakdown voltage may be increased, and parasitic effects with adjacent junctions may be reduced.
摘要翻译： 双极结型晶体管可以用作半导体存储器的选择器件。 双极结晶体管可以由基极和集电极层的堆叠形成。 一组平行的沟槽沿着第一方向下降到底部并且沿着第二方向形成在收集器的下方。 沟槽可以用于在每个沟槽中的基底和收集器的暴露部分中形成局部增强植入物。 作为局部增强植入物的结果，在一些实施例中，泄漏电流可能降低，有效电流能力可能更高，增益可能更高，基极电阻可能降低，击穿电压可能增加，并且具有相邻接点的寄生效应 减少
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20.发明申请METHOD FOR MULTILEVEL PROGRAMMING OF PHASE CHANGE MEMORY CELLS USING A PERCOLATION ALGORITHM 有权使用渗透算法进行相位变化记忆细胞多重编程的方法公开(公告)号：US20080151612A1
公开(公告)日：2008-06-26
申请号：US11949598
申请日：2007-12-03
申请人： Fabio Pellizzer , Agostino Pirovano
发明人： Fabio Pellizzer , Agostino Pirovano
CPC分类号： G11C11/5678 , G11C13/0004 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0078 , G11C2013/0083 , G11C2013/009 , G11C2213/79
摘要： A method and apparatus for programming a phase change memory cell is disclosed. A phase change memory cell includes a memory element of a phase change material having a first state, in which the phase change material is crystalline and has a minimum resistance level, a second state in which the phase change material is amorphous and has a maximum resistance level, and a plurality of intermediate states with resistance levels there between. The method includes using programming pulses to program the phase change memory cell in either the set, reset, or one of the intermediate states. To program in the intermediate states, a programming pulse creates a crystalline percolation path having an average diameter through amorphous phase change material and a second programming pulse modifies the diameter of the crystalline percolation path to program the phase change memory cell to the proper current level.
摘要翻译： 公开了一种用于编程相变存储器单元的方法和装置。 相变存储单元包括具有第一状态的相变材料的存储元件，其中所述相变材料是晶体并且具有最小电阻水平，所述相变材料是非晶态且具有最大电阻的第二状态 电平以及其间具有电阻电平的多个中间状态。 该方法包括使用编程脉冲来对置换，复位或中间状态之一的相变存储器单元进行编程。 为了在中间状态进行编程，编程脉冲产生具有通过非晶相变材料的平均直径的结晶渗透路径，而第二编程脉冲修改晶体渗滤路径的直径以将相变存储器单元编程到适当的电流水平。
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