公开(公告)号：US06225679B1

公开(公告)日：2001-05-01

申请号：US09363231

申请日：1999-07-21

Applicant: Richard Fournel ,  Fabrice Marinet

Inventor： Richard Fournel ,  Fabrice Marinet

IPC: H01L2900

CPC classification number: H01L27/0259

Abstract: A structure for the protection of a high-voltage pad includes a lateral bipolar transistor, an N-type diffusion of which, connected to the pad to be protected, is made in an N-type tub with a zone that extends laterally outside the tub in the base. A P-type implantation is made on the entire substrate outside the N-type tub except in the region in which the zone extends.

Abstract translation: 用于保护高压焊盘的结构包括横向双极晶体管，其N型扩散连接到待保护焊盘的N型扩散件制成在具有横向外延伸到槽体的区域的N型槽中 在基地。 除了区域延伸的区域外，在N型桶外的整个基板上进行P型注入。

公开(公告)号：US08779552B2

公开(公告)日：2014-07-15

申请号：US12897231

申请日：2010-10-04

Applicant: Pascal Fornara ,  Fabrice Marinet

Inventor： Pascal Fornara ,  Fabrice Marinet

IPC: H01L29/72

CPC classification number: H01L23/573 ,  H01L21/26506 ,  H01L21/3221 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit chip formed inside and on top of a semiconductor substrate and including: in the upper portion of the substrate, an active portion in which components are formed; and under the active portion and at a depth ranging between 5 and 50 μm from the upper surface of the substrate, an area comprising sites for gettering metal impurities and containing metal atoms at a concentration ranging between 1017 and 1018 atoms/cm3.

Abstract translation: 一种集成电路芯片，形成在半导体衬底的内部和顶部，并且包括：在衬底的上部，形成有部件的有源部分; 并且在活性部分和距离衬底的上表面5至50μm之间的深度范围内，包括用于吸收金属杂质并且含有浓度范围为1017至1018原子/ cm3之间的金属原子的位置的区域。

公开(公告)号：US08453238B2

公开(公告)日：2013-05-28

申请号：US12917792

申请日：2010-11-02

Applicant: Pierre-Yvan Liardet ,  Fabrice Marinet

Inventor： Pierre-Yvan Liardet ,  Fabrice Marinet

IPC: G06F21/00

CPC classification number: H04L9/004 ,  H04L9/0625 ,  H04L2209/08 ,  H04L2209/125

Abstract: A method for protecting a key used, by an electronic circuit, in a symmetrical algorithm for ciphering or deciphering a message, including the steps of complementing to one the key and the message; executing the algorithm twice, respectively with the key and the message and with the key and the message complemented to one, the selection between that of the executions which processes the key and the message and that which processes the key and the message complemented to one being random; and checking the consistency between the two executions.

Abstract translation: 一种用于通过电子电路保护用于加密或解密消息的对称算法中的密钥的方法，包括与密钥和消息中的一个相互补充的步骤; 执行算法两次，分别是密钥和消息，并将密钥和消息补充为1，处理密钥和消息的执行处理与处理密钥和消息的处理之间的选择与之互补 随机; 并检查两个执行之间的一致性。

公开(公告)号：US07889778B2

公开(公告)日：2011-02-15

申请号：US11096758

申请日：2005-03-31

Applicant: Fabrice Marinet ,  Camille Botella

Inventor： Fabrice Marinet ,  Camille Botella

IPC: H04B1/00

CPC classification number: G06F21/77 ,  G06F21/75 ,  G06K19/073 ,  G06K19/07363 ,  H01L23/576 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A circuit for detecting attacks by contacting an integrated circuit chip comprising means for applying a random signal to a first terminal of at least one conductive path formed in at least one first metallization level of the chip, means for comparing the applied signal with a signal present on a second terminal of the path, and means for delaying the comparison time with respect to the application time, of a duration longer than or equal to the propagation delay through the first path.

Abstract translation: 一种用于通过接触集成电路芯片来检测攻击的电路，包括用于将随机信号施加到形成在芯片的至少一个第一金属化级中的至少一个导电路径的第一端子的装置，用于将所施加的信号与存在的信号进行比较 在路径的第二终端上，以及用于延迟相对于应用时间的比较时间的持续时间长于或等于通过第一路径的传播延迟的持续时间。

公开(公告)号：US07706529B2

公开(公告)日：2010-04-27

申请号：US09995258

申请日：2001-11-27

Applicant: Fabrice Marinet ,  Alexandre Malherbe

Inventor： Fabrice Marinet ,  Alexandre Malherbe

IPC: H04L9/00 ,  H01L27/088 ,  H01L27/008

CPC classification number: G06F7/588 ,  G06K19/073 ,  G06K19/07363 ,  H03K3/84

Abstract: A random signal generator uses a folded MOS transistor, whose drain-source current includes a random component, as an electronic noise source. The random signal generator generates a random binary signal from the random component. The invention may be applied, in particular, to smart cards.

Abstract translation: 随机信号发生器使用其漏源电流包括随机分量的折叠MOS晶体管作为电子噪声源。 随机信号发生器从随机分量生成随机二进制信号。 本发明特别可以应用于智能卡。

公开(公告)号：US06997606B2

公开(公告)日：2006-02-14

申请号：US10325491

申请日：2002-12-19

Applicant: Fabrice Marinet ,  Benjamin Duval

Inventor： Fabrice Marinet ,  Benjamin Duval

IPC: G01K7/00 ,  G01K7/01

CPC classification number: G01K3/005 ,  G01K15/00

Abstract: An integrated temperature sensor delivers threshold detection signals when temperature thresholds have been exceeded. The temperature sensor includes a circuit for detecting a first temperature threshold having a first detection threshold, and for detecting a second temperature threshold having a second detection threshold. The circuit also detects a third temperature threshold between the first and second temperature thresholds, and detects a fourth temperature threshold between the first and second temperature thresholds. The third temperature threshold has a third detection threshold linked with the first detection threshold so that a deviation of the first detection threshold causes a corresponding deviation of the third detection threshold. Similarly, the fourth temperature has a fourth detection threshold linked with the second detection threshold so that a deviation of the second detection threshold causes a corresponding deviation of the fourth detection threshold. The third and fourth temperature thresholds define a temperature window to test the temperature sensor for detecting a deviation of the first and second detection thresholds.

公开(公告)号：US5943264A

公开(公告)日：1999-08-24

申请号：US067494

申请日：1998-04-27

Applicant: Richard Fournel ,  Fabrice Marinet

Inventor： Richard Fournel ,  Fabrice Marinet

IPC: G11C17/16 ,  G11C16/04

CPC classification number: G11C17/16

Abstract: A memory cell in an integrated circuit using CMOS technology includes the following in series: an N type selection MOS transistor and a PN semiconductor junction. The source of the transistor is connected to the N type zone of the junction by a metal contact made on at least a part of the N type zone. The method of control includes, in the programming mode, the application to the integrated circuit of a level of supply voltage greater than a nominal value, within an upper limit that is permissible for the integrated circuit, and the application of this level to the drain and the gate of the selection transistor. The selection transistor is made with a channel having a length smaller than or equal to the minimum length in the technology considered. Accordingly, the selection transistor is biased in the snap-back mode. The memory cell may be used in a memory circuit in matrix form.

Abstract translation: 使用CMOS技术的集成电路中的存储单元包括以下串联：N型选择MOS晶体管和PN半导体结。 晶体管的源极通过在N型区域的至少一部分上形成的金属接触而连接到接合部的N型区域。 控制方法包括在编程模式下，在集成电路允许的上限范围内将集成电路的电源电压大于标称值的应用，以及将该电平应用于漏极 和选择晶体管的栅极。 选择晶体管由所考虑的技术中具有长度小于或等于最小长度的沟道制成。 因此，选择晶体管在快速恢复模式下被偏置。 存储单元可以以矩阵形式用于存储器电路。

公开(公告)号：US09323941B2

公开(公告)日：2016-04-26

申请号：US12942557

申请日：2010-11-09

Applicant: Fabrice Marinet ,  Mathieu Lisart

Inventor： Fabrice Marinet ,  Mathieu Lisart

IPC: G06F11/30 ,  G06F12/14 ,  H04L29/06 ,  G06F21/62 ,  G06F21/78 ,  G06F11/14 ,  G06F21/77

CPC classification number: H04L9/088 ,  G06F3/0623 ,  G06F3/0644 ,  G06F3/0688 ,  G06F11/1458 ,  G06F12/1408 ,  G06F21/62 ,  G06F21/77 ,  G06F21/78 ,  G06F2212/402

Abstract: The component comprises a first memory (MM) comprising a first portion (P1) having a content modified with a first modification entity (K1) and a second portion (P2) having a content modified with a second entity (K2), a storage means (MS) configured to store the first entity (K1) secretly, a non-volatile memory (NVM) storing an item of entity information representative of the second entity (K2) in a location (END) designated by a first indication (INDK2) contained in the said first portion of the first memory.

Abstract translation: 该组件包括第一存储器（MM），其包括具有由第一修改实体（K1）修改的内容的第一部分（P1）和具有用第二实体（K2）修改的内容的第二部分（P2），存储装置 （MS）被配置为秘密地存储第一实体（K1），非易失性存储器（NVM）将代表第二实体（K2）的实体信息项存储在由第一指示（INDK2）指定的位置（END）中， 包含在第一存储器的所述第一部分中。

公开(公告)号：US08592288B2

公开(公告)日：2013-11-26

申请号：US13615104

申请日：2012-09-13

Applicant: Pascal Fornara ,  Fabrice Marinet

Inventor： Pascal Fornara ,  Fabrice Marinet

IPC: H01L21/326 ,  H01L21/479

CPC classification number: H01L27/101 ,  G11C17/16 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521

Abstract: An integrated circuit including a substrate of a semiconductor material and first metal portions of a first metallization level or of a first via level defining pixels of an image. The pixels are distributed in first pixels, for each of which the first metal portion is connected to the substrate, and in second pixels, for each of which the first metal portion is separated from the substrate by at least one insulating portion.

公开(公告)号：US08434046B2

公开(公告)日：2013-04-30

申请号：US13299267

申请日：2011-11-17

Applicant: Fabrice Marinet

Inventor： Fabrice Marinet

IPC: G06F17/50

CPC classification number: H01L27/0203 ,  G06F17/505 ,  G06F17/5081 ,  G06F2217/02 ,  G06F2217/12 ,  G06F2217/66 ,  Y02P90/265

Abstract: The disclosure relates to a method of fabricating an integrated circuit on a semiconductor chip, the method comprising: designing an architecture of the integrated circuit comprising at least first and second standard cells implementing a same basic function; designing for the standard cell at least first and second cell layouts presenting random differences; designing an integrated circuit layout corresponding to the integrated circuit architecture; fabricating the integrated circuit according to the integrated circuit layout; using the first cell layout to implement the first standard cell in the integrated circuit layout; and using the second cell layout to implement the second standard cell in the integrated circuit layout. The method can be used for protection of an integrated circuit against reverse engineering.

Abstract translation: 本公开涉及一种在半导体芯片上制造集成电路的方法，该方法包括：设计集成电路的架构，该集成电路至少包括实现相同基本功能的第一和第二标准单元; 设计标准单元至少具有随机差异的第一和第二单元布局; 设计对应于集成电路架构的集成电路布局; 根据集成电路布局制造集成电路; 使用第一单元布局来实现集成电路布局中的第一标准单元; 并且使用第二单元布局来实现集成电路布局中的第二标准单元。 该方法可用于保护集成电路免遭逆向工程。