公开(公告)号：US06784076B2

公开(公告)日：2004-08-31

申请号：US10118569

申请日：2002-04-08

申请人： Fernando Gonzalez ,  Chandra Mouli ,  Lyle Jones

发明人： Fernando Gonzalez ,  Chandra Mouli ,  Lyle Jones

IPC分类号： H01L2176

CPC分类号： H01L27/10873 ,  H01L21/26506 ,  H01L21/76235 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/0214 ,  H01L27/10811 ,  H01L27/10844 ,  H01L27/11521 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/7846

摘要： A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region is formed at various process stages according to embodiments. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.

摘要翻译： 公开了一种制造绝缘体上部分硅片的工艺。 在衬底中产生深的注入区域。 在横向腔蚀刻期间，深注入区域抵抗蚀刻。 侧腔蚀刻用于部分隔离深注入区域上方的有效区域。 根据实施例，在各种处理阶段形成深注入区域。 还公开了通过该过程实现的主动装置。 还公开了一种使用有源器件的系统。

公开(公告)号：US06686636B2

公开(公告)日：2004-02-03

申请号：US10008650

申请日：2001-11-09

申请人： Fernando Gonzalez ,  Chandra Mouli

发明人： Fernando Gonzalez ,  Chandra Mouli

IPC分类号： H01L2710

CPC分类号： H01L29/4991 ,  H01L21/28512 ,  H01L21/7682 ,  H01L21/76895 ,  H01L23/5226 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/4983 ,  H01L29/66492 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system comprising a memory device that includes at least one semiconductor structure wherein the semiconductor structure includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping layer in communication with at least a portion of the gate and the drain, a first portion of a gate oxide region in communication with at least a portion of the gate and the source, a second portion of a gate oxide region in communication with at least a portion of the gate and the drain. The source, the gate, the first capping layer, and the first portion of a gate oxide region define a first gap. The drain, the gate, the second capping layer, and the second portion of a gate oxide region define a second gap. The semiconductor structure also includes a first junction area located beneath the first gap, the gate and the source and a second junction area located beneath the second gap, the gate and the drain. The system also includes a processor and a bus connecting the processor and the memory device.

摘要翻译： 一种包括存储器件的系统，其包括至少一个半导体结构，其中所述半导体结构包括升高的源极，升高的漏极，位于所述源极和漏极之间的栅极，与所述栅极的至少一部分连通的第一覆盖层 源极，与栅极和漏极的至少一部分连通的第二覆盖层，与栅极和源极的至少一部分连通的栅极氧化物区域的第一部分，栅极的第二部分 氧化物区域与栅极和漏极的至少一部分连通。 源极，栅极，第一覆盖层和栅极氧化物区域的第一部分限定第一间隙。 漏极，栅极，第二覆盖层和栅极氧化物区域的第二部分限定第二间隙。 半导体结构还包括位于第一间隙下方的第一结区域，栅极和源极以及位于第二间隙下方的第二结区域，栅极和漏极。 该系统还包括处理器和连接处理器和存储器件的总线。

公开(公告)号：US06559032B2

公开(公告)日：2003-05-06

申请号：US09888929

申请日：2001-06-25

申请人： Fernando Gonzalez ,  Chandra Mouli

发明人： Fernando Gonzalez ,  Chandra Mouli

IPC分类号： H01L2176

CPC分类号： H01L21/76205 ,  H01L21/76202 ,  H01L27/10805 ,  H01L27/10811 ,  H01L27/10844 ,  H01L27/10873

摘要： A method of forming an isolated structure of sufficient size to permit the fabrication of an active device thereon is comprised of the steps of depositing a gate oxide layer on a substrate. Material, such as a polysilicon layer and a nitride layer, is deposited on the gate oxide layer to protect the gate oxide layer. An active area is defined, typically by patterning a layer of photoresist. The protective material, the layer of oxide, and finally the substrate are etched to form a trench around the active area. Spacers are formed on the sides of the active area. The substrate is etched to deepen the trench around the active area to a point below the spacers. The substrate is oxidized at the bottom of the trench and horizontally under the active area to at least partially isolate the active area from the substrate. Oxide spacers are formed on the sides of the active area to fill exposed curved oxide regions and the remainder of the trench may be filled with an oxide.

公开(公告)号：US6110798A

公开(公告)日：2000-08-29

申请号：US22024

申请日：1998-02-11

申请人： Fernando Gonzalez ,  Chandra Mouli

发明人： Fernando Gonzalez ,  Chandra Mouli

IPC分类号： H01L21/762 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/76205 ,  H01L21/76202 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10873 ,  H01L27/10811

摘要： A method of forming an isolated structure of sufficient size to permit the fabrication of an active device thereon is comprised of the steps of depositing a gate oxide layer on a substrate. Material, such as a polysilicon layer and a nitride layer, is deposited on the gate oxide layer to protect the gate oxide layer. An active area is defined, typically by patterning a layer of photoresist. The protective material, the layer of oxide, and finally the substrate are etched to form a trench around the active area. Spacers are formed on the sides of the active area. The substrate is etched to deepen the trench around the active area to a point below the spacers. The substrate is oxidized at the bottom of the trench and horizontally under the active area to at least partially isolate the active area from the substrate. Oxide spacers are formed on the sides of the active area to fill exposed curved oxide regions and the remainder of the trench may be filled with an oxide.

公开(公告)号：US08084322B2

公开(公告)日：2011-12-27

申请号：US11440260

申请日：2006-05-24

申请人： Fernando Gonzalez ,  Chandra Mouli

发明人： Fernando Gonzalez ,  Chandra Mouli

IPC分类号： H01L21/8242

CPC分类号： H01L29/66636 ,  H01L21/2257 ,  H01L21/823481 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/7834

摘要： Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.

摘要翻译： 用于形成诸如晶体管的器件的技术具有垂直的接合边缘。 更具体地说，在沟槽中形成浅沟槽并填充氧化物。 可以在氧化物中形成空穴并填充导电材料，例如掺杂的多晶硅。 在沟槽边缘处在多晶硅和暴露的衬底之间形成垂直结，使得在热循环期间，掺杂多晶硅将掺杂元素扩散到相邻的单晶硅中，有利地形成具有期望性质的二极管延伸。

公开(公告)号：US20060292766A1

公开(公告)日：2006-12-28

申请号：US11458967

申请日：2006-07-20

申请人： Fernando Gonzalez ,  Chandra Mouli ,  Lyle Jones

发明人： Fernando Gonzalez ,  Chandra Mouli ,  Lyle Jones

IPC分类号： H01L21/84 ,  H01L29/76

CPC分类号： H01L27/10873 ,  H01L21/26506 ,  H01L21/76235 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/0214 ,  H01L27/10811 ,  H01L27/10844 ,  H01L27/11521 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/7846

摘要： A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region is formed at various process stages according to embodiments. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.

公开(公告)号：US20060240637A1

公开(公告)日：2006-10-26

申请号：US11472950

申请日：2006-06-21

申请人： Kunal Parekh ,  Chandra Mouli ,  M. Roberts ,  Fernando Gonzalez

发明人： Kunal Parekh ,  Chandra Mouli ,  M. Roberts ,  Fernando Gonzalez

IPC分类号： H01L21/76 ,  H01L21/31

CPC分类号： H01L21/76801 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/785

摘要： The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor construction is passivated by subjecting the construction to an anneal at a temperature of greater than or equal to 350° C. while exposing the construction to a deuterium-enriched ambient.

公开(公告)号：US06958519B2

公开(公告)日：2005-10-25

申请号：US09956171

申请日：2001-09-18

申请人： Fernando Gonzalez ,  Chandra Mouli

发明人： Fernando Gonzalez ,  Chandra Mouli

IPC分类号： H01L27/07 ,  H01L29/76

CPC分类号： H01L27/0727

摘要： Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a body. A first resistive element is received by the substrate and connected between the transistor's gate and the body. A second resistive element is received by the substrate and connected between the body and a reference voltage node. The first and second resistive elements form a voltage divider which is configured to selectively change threshold voltages of the field effect transistor with state changes in the gate voltage. In a preferred embodiment, first and second diode assemblies are positioned over the substrate and connected between the gate and body, and the body and a reference voltage node to provide the voltage divider.

摘要翻译： 描述形成场效应晶体管和合成的场效应晶体管电路的方法。 在一个实施例中，半导体衬底包括具有主体的场效应晶体管。 第一电阻元件由衬底接收并连接在晶体管的栅极和主体之间。 第二电阻元件由衬底接收并连接在主体和参考电压节点之间。 第一和第二电阻元件形成分压器，其被配置为选择性地改变场效应晶体管的阈值电压，栅极电压的状态变化。 在优选实施例中，第一和第二二极管组件位于衬底上并且连接在栅极和主体之间，以及主体和参考电压节点以提供分压器。

公开(公告)号：US06683355B2

公开(公告)日：2004-01-27

申请号：US10008654

申请日：2001-11-09

申请人： Fernando Gonzalez ,  Chandra Mouli

发明人： Fernando Gonzalez ,  Chandra Mouli

IPC分类号： H01L2710

CPC分类号： H01L29/4991 ,  H01L21/28512 ,  H01L21/7682 ,  H01L21/76895 ,  H01L23/5226 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/4983 ,  H01L29/66492 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system comprising a memory device that includes at least one semiconductor structure wherein the semiconductor structure includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping layer in communication with at least a portion of the gate and the drain, a first portion of a gate oxide region in communication with at least a portion of the gate and the source, a second portion of a gate oxide region in communication with at least a portion of the gate and the drain. The source, the gate, the first capping layer, and the first portion of a gate oxide region define a first gap. The drain, the gate, the second capping layer, and the second portion of a gate oxide region define a second gap. The semiconductor structure also includes a first junction area located beneath the first gap, the gate and the source and a second junction area located beneath the second gap, the gate and the drain. The system also includes a processor and a bus connecting the processor and the memory device.

公开(公告)号：US06596606B2

公开(公告)日：2003-07-22

申请号：US10008652

申请日：2001-11-09

申请人： Fernando Gonzalez ,  Chandra Mouli

发明人： Fernando Gonzalez ,  Chandra Mouli

IPC分类号： H01L2176

CPC分类号： H01L29/4991 ,  H01L21/28512 ,  H01L21/7682 ,  H01L21/76895 ,  H01L23/5226 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/4983 ,  H01L29/66492 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor structure which includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping layer in communication with at least a portion of the gate and the drain, a first portion of a gate oxide region in communication with at least a portion of the gate and the source, a second portion of a gate oxide region in communication with at least a portion of the gate and the drain. The source, the gate, the first capping layer, and the first portion of a gate oxide region define a first gap. The drain, the gate, the second capping layer, and the second portion of a gate oxide region define a second gap. The structure also includes a first junction area located beneath the first gap, the gate and the source and a second junction area located beneath the second gap, the gate and the drain.

摘要翻译： 一种形成半导体结构的方法，该半导体结构包括凸起源，高漏极，位于源极和漏极之间的栅极，与栅极和源极的至少一部分连通的第一覆盖层，第二覆盖层， 与栅极和漏极的至少一部分的通信，与栅极和源极的至少一部分连通的栅极氧化物区域的第一部分，栅极氧化物区域的与至少一部分连通的第二部分 的门和排水沟。 源极，栅极，第一覆盖层和栅极氧化物区域的第一部分限定第一间隙。 漏极，栅极，第二覆盖层和栅极氧化物区域的第二部分限定第二间隙。 该结构还包括位于第一间隙下方的第一接合区域，栅极和源极以及位于第二间隙下方的栅极和漏极的第二接合区域。