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公开(公告)号：US06411553B1
公开(公告)日：2002-06-25
申请号：US09653249
申请日：2000-08-31
IPC分类号： G11C700
CPC分类号： G11C7/1048
摘要： A method and apparatus for biasing an open ended bus line to a predetermined voltage just prior to the arrival of a data signal. The bias on the bus line is used to move the voltage of a received data signal closer to trip points used to determine the logical value of the data signals. The equilibration circuit may be are enabled by a clock signal derived from a sense amplifier clock signal to ensure that the bias voltage is applied to the bus line just prior to the arrival of the data signal.
摘要翻译： 一种用于在数据信号到达之前将开路总线线路偏压到预定电压的方法和装置。 总线上的偏置用于将接收到的数据信号的电压更接近用于确定数据信号的逻辑值的跳变点。 平衡电路可以通过从读出放大器时钟信号导出的时钟信号来实现，以确保在数据信号到达之前将偏压施加到总线上。
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公开(公告)号：US06178501B1
公开(公告)日：2001-01-23
申请号：US09069486
申请日：1998-04-28
申请人： Charles L. Ingalls
发明人： Charles L. Ingalls
IPC分类号： G06F15177
CPC分类号： G11C7/20 , G11C7/1045 , G11C7/1072 , G11C11/4072
摘要： An SDRAM is initialized with an initialization pulse generated in response to a load mode register command that is generated to program a mode register in the SDRAM. Antifuse circuits are read and registers are initialized according to the initialization pulse each time the mode register is programmed. The mode register is programmed in a boot up procedure and in subsequent reboot procedures of a computer system including the SDRAM.
摘要翻译： 通过响应于为SDRAM中的模式寄存器编程而产生的负载模式寄存器命令产生的初始化脉冲来初始化SDRAM。 每次模式寄存器被编程时，读取消声电路并根据初始化脉冲对寄存器进行初始化。 在引导过程中以及包括SDRAM的计算机系统的后续重新启动过程中对模式寄存器进行编程。
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公开(公告)号：US5978285A
公开(公告)日：1999-11-02
申请号：US92392
申请日：1998-06-05
申请人： Charles L. Ingalls
发明人： Charles L. Ingalls
CPC分类号： G11C7/1057 , G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/22 , H03K5/133
摘要： A delay is introduced into the output path of a synchronous device in response to a rising supply voltage. Specifically, as its supply voltage rises, a synchronous memory device may operate too quickly, particularly data output. To slow the rate at which the memory device outputs data, the clock which controls the data output rate is delayed by an amount correlative to the magnitude of the supply voltage.
摘要翻译： 响应于上升的电源电压，延迟被引入到同步装置的输出路径中。 具体来说，随着其电源电压上升，同步存储器件可能运行得太快，特别是数据输出。 为了减慢存储器件输出数据的速率，控制数据输出速率的时钟被延迟与电源电压的大小相关的量。
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14.发明授权Method and apparatus for global testing the impedance of a programmable element 失效用于全局测试可编程元件阻抗的方法和装置
公开(公告)号：US5892716A
公开(公告)日：1999-04-06
申请号：US90258
申请日：1998-06-04
申请人： Charles L. Ingalls
发明人： Charles L. Ingalls
摘要： A unique latch circuitry having both a latching and margin testing capability is provided. Every antifuse in a memory circuit is connected to a respective latch circuit. The latch circuits utilize a global input signal to configure a reference impedance with either a normal operational mode impedance or a test mode impedance. Once configured, and without any other additional circuitry, the latch circuits are capable of performing the latching or testing capability based upon comparisons to the reference impedance. When configured for the normal operational mode, the latch circuits read and output the status of their respective antifuses responsive to a control signal. When configured for the testing mode, the latch circuits test the impedance margin of their respective antifuses responsive to the same control signal. The configuration of the unique latch circuit, and the use of the same control signal for normal and test modes, allows for the global testing of all of the antifuses in a memory circuit while reducing the circuitry required to perform the testing. In addition, it is also possible to have different reference impedances for the normal and test modes.
摘要翻译： 提供了具有锁存和边缘测试能力的独特锁存电路。 存储器电路中的每个反熔丝连接到相应的锁存电路。 锁存电路利用全局输入信号来配置具有正常工作模式阻抗或测试模式阻抗的参考阻抗。 一旦被配置，并且没有任何其他附加电路，锁存电路能够基于与参考阻抗的比较来执行锁存或测试能力。 当配置为正常操作模式时，锁存电路响应于控制信号读取并输出它们各自的反熔丝的状态。 当配置为测试模式时，锁存电路根据相同的控制信号测试其各自的反熔丝的阻抗余量。 唯一锁存电路的配置以及对正常和测试模式使用相同的控制信号允许全面测试存储器电路中的所有反熔丝，同时减少执行测试所需的电路。 另外，正常和测试模式也可能有不同的参考阻抗。
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公开(公告)号：US5442642A
公开(公告)日：1995-08-15
申请号：US989403
申请日：1992-12-11
IPC分类号： G01R31/3185 , G06F11/267 , G06F11/27 , G11C29/14 , H04B17/00
CPC分类号： G01R31/318505 , G06F11/267 , G06F11/27 , G11C29/14
摘要： A test system is added to a substrate and a test mode of operation is added to the timing and control functions of a system on the substrate. When a multifunctional system on the substrate is tested, a first functional subsystem is connected to an external tester. The tester causes the timing and control system to enter the test mode of operation. When in the test mode of operation, the test system provides a signal derived from a signal generator on the substrate. The generated signal is coupled to a second functional subsystem so that functional independence of the first and second subsystems can be verified.
摘要翻译： 将测试系统添加到衬底中，并且将测试操作模式添加到衬底上的系统的定时和控制功能。 当测试基板上的多功能系统时，第一功能子系统连接到外部测试器。 测试仪使定时和控制系统进入测试操作模式。 当处于测试操作模式时，测试系统提供从基板上的信号发生器得到的信号。 所生成的信号耦合到第二功能子系统，使得能够验证第一和第二子系统的功能独立性。
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公开(公告)号：US20180315467A1
公开(公告)日：2018-11-01
申请号：US15963663
申请日：2018-04-26
IPC分类号： G11C11/4091 , G11C11/56
摘要： A sensing system can read from a memory cell configured to store a data bit and to produce a differential signal indicating a data state of the memory cell. The data state can be selected from three data states. An example of the system can include a pair of bit lines, a pair of sense amplifiers (SAs), and a data output circuit. The bit lines are coupled to the memory cell to receive the differential signal. The SAs are each independently coupled to the bit lines through an isolation circuit. The data output circuit can receive outputs from the SAs and indicate the data state of the memory cell based on the outputs.
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公开(公告)号：US07986578B2
公开(公告)日：2011-07-26
申请号：US12621394
申请日：2009-11-18
申请人： Tae Kim , Charles L. Ingalls , David Pinney , Howard Kirsch
发明人： Tae Kim , Charles L. Ingalls , David Pinney , Howard Kirsch
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/065 , G11C7/12 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2207/2227
摘要： Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier. The data state is latched in response to the driving voltages. In coupling the digit line to a sense amplifier, the digit line is coupled to the sense amplifier for a first time period and decoupled from the sense amplifier for a second time period. The digit line is coupled to the sense amplifier at a controlled rate following the second time period.
摘要翻译： 感测耦合到数字线并且将数字线耦合到读出放大器的数据状态的系统和方法。 在感测耦合到数字线的数据状态时，数字线耦合到感测节点并且提供给读出放大器的驱动电压。 响应于驱动电压而锁存数据状态。 在将数字线耦合到读出放大器时，数字线在第一时间段耦合到读出放大器，并在第二时间段内从读出放大器去耦。 数字线以跟随第二时间段的受控速率耦合到读出放大器。
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公开(公告)号：US20100061158A1
公开(公告)日：2010-03-11
申请号：US12621394
申请日：2009-11-18
申请人： Tae Kim , Charles L. Ingalls , David Pinney , Howard Kirsch
发明人： Tae Kim , Charles L. Ingalls , David Pinney , Howard Kirsch
CPC分类号： G11C7/08 , G11C7/065 , G11C7/12 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2207/2227
摘要： Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier. The data state is latched in response to the driving voltages. In coupling the digit line to a sense amplifier, the digit line is coupled to the sense amplifier for a first time period and decoupled from the sense amplifier for a second time period. The digit line is coupled to the sense amplifier at a controlled rate following the second time period.
摘要翻译： 感测耦合到数字线并且将数字线耦合到读出放大器的数据状态的系统和方法。 在感测耦合到数字线的数据状态时，数字线耦合到感测节点并且提供给读出放大器的驱动电压。 响应于驱动电压而锁存数据状态。 在将数字线耦合到读出放大器时，数字线在第一时间段耦合到读出放大器，并在第二时间段内与读出放大器去耦。 数字线以跟随第二时间段的受控速率耦合到读出放大器。
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公开(公告)号：US07626877B2
公开(公告)日：2009-12-01
申请号：US12399757
申请日：2009-03-06
申请人： Tae Kim , Charles L. Ingalls , David Pinney , Howard Kirsch
发明人： Tae Kim , Charles L. Ingalls , David Pinney , Howard Kirsch
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/065 , G11C7/12 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2207/2227
摘要： Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier. The data state is latched in response to the driving voltages. In coupling the digit line to a sense amplifier, the digit line is coupled to the sense amplifier for a first time period and decoupled from the sense amplifier for a second time period. The digit line is coupled to the sense amplifier at a controlled rate following the second time period.
摘要翻译： 感测耦合到数字线并且将数字线耦合到读出放大器的数据状态的系统和方法。 在感测耦合到数字线的数据状态时，数字线耦合到感测节点并且提供给读出放大器的驱动电压。 响应于驱动电压而锁存数据状态。 在将数字线耦合到读出放大器时，数字线在第一时间段耦合到读出放大器，并在第二时间段内从读出放大器去耦。 数字线以跟随第二时间段的受控速率耦合到读出放大器。
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公开(公告)号：US07460430B2
公开(公告)日：2008-12-02
申请号：US11497176
申请日：2006-08-01
IPC分类号： G11C8/00
CPC分类号： G11C8/08
摘要： Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that adjacent wordlines are driven by wordline drivers enabled by different row decoders. Each wordline driver includes a weak transistor to ground and a strong transistor to ground. By disabling the wordline driver on the wordlines directly adjacent to the active wordlines, a path is provided to drive the coupling noise from the active wordline to ground through the strong transistor.
摘要翻译： 配置为减少存储器阵列中相邻字线之间的耦合噪声的存储器件。 更具体地说，字线驱动器被交错，使得相邻字线由不同行解码器启用的字线驱动器驱动。 每个字线驱动器包括一个微弱的晶体管接地和一个强大的晶体管接地。 通过禁用与有源字线直接相邻的字线上的字线驱动器，提供一个路径，以通过强晶体管驱动从有源字线到地的耦合噪声。
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