公开(公告)号：US11664928B2

公开(公告)日：2023-05-30

申请号：US17453926

申请日：2021-11-08

Applicant: Futurewei Technologies, Inc.

Inventor： Gleb Vyacheslavovich Kalachev ,  Ivan Leonidovich Mazurenko ,  Pavel Anatolyevich Panteleev ,  Elyar Eldarovich Gasanov ,  Aleksey Alexandrovich Letunovskiy ,  Wen Tong ,  Carmela Cozzo

IPC: H04L1/00 ,  H03M13/11 ,  H03M13/03 ,  H03M13/00

CPC classification number: H04L1/0057 ,  H03M13/036 ,  H03M13/116 ,  H03M13/1165 ,  H03M13/616 ,  H03M13/618 ,  H03M13/6362 ,  H03M13/6516 ,  H04L1/005 ,  H04L1/0041 ,  H04L1/0063 ,  H04L1/0068

Abstract: A method for generating a code, a method for encoding and decoding data, and an encoder and a decoder performing the encoding and decoding are disclosed. In an embodiment, a method for lifting a child code from a base code for encoding and decoding data includes determining a single combination of a circulant size, a lifting function, and a labelled base matrix PCM according to an information length and a code rate using data stored in a lifting table. The lifting table was defined at a code generation stage. The method also includes calculating a plurality of shifts for the child code. Each shift is calculated by applying the lifting function to the labelled base matrix PCM with a defined index using the circulant size and using the derived child PCM to encode or decode data.

公开(公告)号：US11171742B2

公开(公告)日：2021-11-09

申请号：US16899248

申请日：2020-06-11

Applicant: Futurewei Technologies, Inc.

Inventor： Gleb Vyacheslavovich Kalachev ,  Ivan Leonidovich Mazurenko ,  Pavel Anatolyevich Panteleev ,  Elyar Eldarovich Gasanov ,  Aleksey Alexandrovich Letunovskiy ,  Wen Tong ,  Carmela Cozzo

IPC: H04L1/00 ,  H03M13/11 ,  H03M13/03 ,  H03M13/00

Abstract: A method for generating a code, a method for encoding and decoding data, and an encoder and a decoder performing the encoding and decoding are disclosed. In an embodiment, a method for lifting a child code from a base code for encoding and decoding data includes determining a single combination of a circulant size, a lifting function, and a labelled base matrix PCM according to an information length and a code rate using data stored in a lifting table. The lifting table was defined at a code generation stage. The method also includes calculating a plurality of shifts for the child code. Each shift is calculated by applying the lifting function to the labelled base matrix PCM with a defined index using the circulant size and using the derived child PCM to encode or decode data.

公开(公告)号：US20160028462A1

公开(公告)日：2016-01-28

申请号：US14874190

申请日：2015-10-02

Applicant: Futurewei Technologies, Inc.

Inventor： Jianglei Ma ,  Peiying Zhu ,  Wen Tong ,  Ming Jia

IPC: H04B7/06 ,  H04B7/02 ,  H04B7/04

CPC classification number: H04B7/0617 ,  H01Q25/00 ,  H04B7/024 ,  H04B7/0456 ,  H04B7/0632 ,  H04B7/0639 ,  H04W8/24 ,  H04W48/08 ,  H04W88/08

Abstract: In accordance with an embodiment, a method of operating a base station configured to communicate with at least one user device includes transmitting a reference signal to the at least one user device, receiving channel quality information from the at least one user device, and forming a beam based on the channel quality information received from the at least one user device.

Abstract translation: 根据一个实施例，一种操作配置成与至少一个用户设备进行通信的基站的方法包括：向所述至少一个用户设备发送参考信号，从所述至少一个用户设备接收信道质量信息，以及形成 基于从至少一个用户设备接收的信道质量信息。

公开(公告)号：US20150074680A1

公开(公告)日：2015-03-12

申请号：US14480561

申请日：2014-09-08

Applicant: Futurewei Technologies Inc.

Inventor： Qifan Zhang ,  Yiqun Ge ,  Wuxian Shi ,  Tao Huang ,  Wen Tong

IPC: G06F9/50 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F1/08 ,  G06F1/10 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3871 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891 ,  G06F9/5011 ,  G06F15/8007 ,  G06F15/8053 ,  G06F15/8092 ,  G06F2009/3883

Abstract: A method of operating a clock-less asynchronous processing system comprising a plurality of successive asynchronous processing components. The method comprises providing a first token signal path in the plurality of processing components to allow propagation of a token through the processing components. Possession of the token by one of the processing components enables the processing component to conduct a transaction with a resource component that is shared among the processing components. The method comprises propagating the token from one processing component to another processing component along the token signal path.

Abstract translation: 一种操作包括多个连续的异步处理组件的无时钟异步处理系统的方法。 该方法包括在多个处理组件中提供第一令牌信号路径以允许令牌通过处理组件传播。 通过其中一个处理组件拥有令牌使处理组件能够与处理组件之间共享的资源组件进行交易。 该方法包括沿令牌信号路径将令牌从一个处理组件传播到另一个处理组件。

公开(公告)号：US20150074380A1

公开(公告)日：2015-03-12

申请号：US14480556

申请日：2014-09-08

Applicant: Futurewei Technologies Inc.

Inventor： Tao Huang ,  Yiqun Ge ,  Qifan Zhang ,  Wuxian Shi ,  Wen Tong

IPC: G06F9/38

CPC classification number: G06F9/30145 ,  G06F1/08 ,  G06F1/10 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3871 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891 ,  G06F9/5011 ,  G06F15/8007 ,  G06F15/8053 ,  G06F15/8092 ,  G06F2009/3883

Abstract: A clock-less asynchronous processor comprising a plurality of parallel asynchronous processing logic circuits, each processing logic circuit configured to generate an instruction execution result. The processor comprises an asynchronous instruction dispatch unit coupled to each processing logic circuit, the instruction dispatch unit configured to receive multiple instructions from memory and dispatch individual instructions to each of the processing logic circuits. The processor comprises a crossbar coupled to an output of each processing logic circuit and to the dispatch unit, the crossbar configured to store the instruction execution results.

Abstract translation: 一种包括多个并行异步处理逻辑电路的无时钟异步处理器，每个处理逻辑电路经配置以产​​生指令执行结果。 处理器包括耦合到每个处理逻辑电路的异步指令调度单元，所述指令调度单元被配置为从存储器接收多个指令，并向每个处理逻辑电路发送单独的指令。 处理器包括耦合到每个处理逻辑电路的输出的交叉开关和分配单元，该交叉开关被配置为存储指令执行结果。

公开(公告)号：US20150074378A1

公开(公告)日：2015-03-12

申请号：US14480541

申请日：2014-09-08

Applicant: Futurewei Technologies, Inc.

Inventor： Yiqun Ge ,  Wuxian Shi ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/3001 ,  G06F9/30145 ,  G06F9/3838 ,  G06F9/3871

Abstract: Embodiments are provided for an asynchronous processor with heterogeneous processors. In an embodiment, the apparatus for an asynchronous processor comprises a memory configured to cache instructions, and a first unit (XU) configured to processing a first instruction of the instructions. The apparatus also comprises a second XU having less restricted access than the first XU to a resource of the asynchronous processor and configured to process a second instruction of the instructions. The second instruction requires access to the resource. The apparatus further comprises a feedback engine configured to decode the first instruction and the second instruction, and issue the first instruction to the first XU, and a scheduler configured to send the second instruction to the second XU.

Abstract translation: 为具有异构处理器的异步处理器提供实施例。 在一个实施例中，用于异步处理器的装置包括被配置为缓存指令的存储器以及被配置为处理指令的第一指令的第一单元（XU）。 所述装置还包括第二XU，其具有比所述第一XU更少受限于所述异步处理器的资源的访问，并被配置为处理所述指令的第二指令。 第二条指令需要访问资源。 所述装置还包括被配置为对所述第一指令和所述第二指令进行解码并且向所述第一XU发出所述第一指令的反馈引擎，以及被配置为向所述第二XU发送所述第二指令的调度器。

公开(公告)号：US20150074377A1

公开(公告)日：2015-03-12

申请号：US14477536

申请日：2014-09-04

Applicant: Futurewei Technologies, Inc.

Inventor： Wuxian Shi ,  Yiqun Ge ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

IPC: G06F9/38

CPC classification number: G06F9/3871 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3885 ,  G06F9/4494

Abstract: Embodiments are provided for an asynchronous processor with pipelined arithmetic and logic unit. The asynchronous processor includes a non-transitory memory for storing instructions and a plurality of instruction execution units (XUs) arranged in a ring architecture for passing tokens. Each one of the XUs comprises a logic circuit configured to fetch a first instruction from the non-transitory memory, and execute the first instruction. The logic circuit is also configured to fetch a second instruction from the non-transitory memory, and execute the second instruction, regardless whether the one of the XUs holds a token for writing the first instruction. The logic circuit is further configured to write the first instruction to the non-transitory memory after fetching the second instruction.

Abstract translation: 为具有流水线算术和逻辑单元的异步处理器提供实施例。 异步处理器包括用于存储指令的非暂存存储器和布置在用于传递令牌的环形架构中的多个指令执行单元（XU）。 XU中的每一个包括被配置为从非暂时存储器获取第一指令并执行第一指令的逻辑电路。 逻辑电路还被配置为从非瞬时存储器获取第二指令，并且执行第二指令，而不管XU中的一个是否存储用于写入第一指令的令牌。 逻辑电路还被配置为在获取第二指令之后将第一指令写入非暂时存储器。

公开(公告)号：US20150074376A1

公开(公告)日：2015-03-12

申请号：US14480562

申请日：2014-09-08

Applicant: Futurewei Technologies, Inc.

Inventor： Yiqun Ge ,  Wuxian Shi ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

IPC: G06F15/82 ,  G06F9/30

CPC classification number: G06F15/825 ,  G06F9/30058 ,  G06F9/38 ,  G06F9/3842 ,  G06F9/3861 ,  G06F9/3869 ,  G06F9/3871

Abstract: Embodiments are provided for an asynchronous processor using master and assisted tokens. In an embodiment, an apparatus for an asynchronous processor comprises a memory to cache a plurality of instructions, a feedback engine to decode the instructions from the memory, and a plurality of XUs coupled to the feedback engine and arranged in a token ring architecture. Each one of the XUs is configured to receive an instruction of the instructions form the feedback engine, and receive a master token associated with a resource and further receive an assisted token for the master token. Upon determining that the assisted token and the master token are received in an abnormal order, the XU is configured to detect an operation status for the instruction in association with the assisted token, and upon determining a needed action in accordance with the operation status and the assisted token, perform the needed action.

Abstract translation: 为使用主和辅助令牌的异步处理器提供实施例。 在一个实施例中，用于异步处理器的装置包括用于高速缓存多个指令的存储器，用于对来自存储器的指令进行解码的反馈引擎，以及耦合到反馈引擎并以令牌环结构排列的多个XU。 每个XU被配置为从反馈引擎接收指令的指令，并且接收与资源相关联的主令牌，并且还接收主令牌的辅助令牌。 在确定以异常顺序接收到辅助令牌和主令牌之后，XU被配置为检测与辅助令牌相关联的指令的操作状态，并且在根据操作状态确定所需动作时， 辅助令牌，执行所需的操作。

公开(公告)号：US20150074445A1

公开(公告)日：2015-03-12

申请号：US14480522

申请日：2014-09-08

Applicant: Futurewei Technologies Inc.

Inventor： Tao Huang ,  Qifan Zhang ,  Wuxian Shi ,  Yiqun Ge ,  Wen Tong

IPC: G06F1/08 ,  G06F1/10

CPC classification number: G06F9/30145 ,  G06F1/08 ,  G06F1/10 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3871 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891 ,  G06F9/5011 ,  G06F15/8007 ,  G06F15/8053 ,  G06F15/8092 ,  G06F2009/3883

Abstract: A clock-less asynchronous processing circuit or system having a plurality of pipelined processing stages utilizes self-clocked generators to tune the delay needed in each of the processing stages to complete the processing cycle. Because different processing stages may require different amounts of time to complete processing or may require different delays depending on the processing required in a particular stage, the self-clocked generators may be tuned to each stage's necessary delay(s) or may be programmably configured.

Abstract translation: 具有多个流水线处理级的无时钟异步处理电路或系统利用自定时发生器来调整每个处理阶段所需的延迟以完成处理周期。 因为不同的处理阶段可能需要不同的时间量来完成处理，或者可能需要根据特定阶段所需的处理而产生不同的延迟，所以自定时发生器可以被调谐到每个阶段的必要延迟或者可以被编程地配置。

公开(公告)号：US20150074382A1

公开(公告)日：2015-03-12

申请号：US14325117

申请日：2014-07-07

Applicant: Futurewei Technologies, Inc.

Inventor： Wuxian Shi ,  Yiqun Ge ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

IPC: G06F9/48

CPC classification number: H04L12/433 ,  G06F9/3871 ,  G06F15/16

Abstract: Embodiments are provided for adding a token jump logic to an asynchronous processor with token passing. The token jump logic allows token forward jumps and token backward jumps over a cascade of token processing logics in the processor. An embodiment method includes determining, using a token jump logic coupled to a cascade of token processing logics, whether to administer a token forward jump or a token backward jump of a token signal passing through the token processing logics. The token forward jump and token backward jump allow the token signal to skip one or more token processing logics in the cascade. The method further includes monitoring, for each of the token processing logics, a polarity status of a token sense logic, and inverting the polarity status according to the determination at the token jump logic.

Abstract translation: 提供了实施例，用令牌传递将令牌跳转逻辑添加到异步处理器。 令牌跳转逻辑允许在处理器中的令牌处理逻辑级联的令牌向前跳跃和令牌向后跳转。 实施例方法包括使用耦合到令牌处理逻辑的级联的令牌跳转逻辑来确定是否管理通过令牌处理逻辑的令牌信号的令牌前向跳转或令牌反向跳转。 令牌向前跳转和令牌反向跳转允许令牌信号跳过级联中的一个或多个令牌处理逻辑。 该方法还包括针对令牌处理逻辑中的每一个监视令牌检测逻辑的极性状态，以及根据令牌跳转逻辑处的确定来反转极性状态。