公开(公告)号：US20180261536A1

公开(公告)日：2018-09-13

申请号：US15453133

申请日：2017-03-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： John H. Zhang ,  Carl J. Radens ,  Lawrence A. Clevenger

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5226

Abstract: The disclosure is directed to an integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a first metal level including a first metal line within a first dielectric layer; a second metal level including a second metal line in a second dielectric layer, the second metal level being over the first metal level; a first via interconnect structure extending through the first metal level and through the second metal level, wherein the first via interconnect structure abuts a first lateral of the first metal line and a first lateral end of the second metal line, and wherein the first via interconnect structure is a vertically uniform structure and includes a first metal.

公开(公告)号：US09640765B2

公开(公告)日：2017-05-02

申请号：US15190365

申请日：2016-06-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lawrence A. Clevenger ,  Chandrasekhar Narayan ,  Gregory A. Northrop ,  Carl J. Radens ,  Brian C. Sapp

IPC: H01L51/00 ,  H01L29/775 ,  H01L29/66 ,  B82Y40/00 ,  B82Y10/00 ,  H01L29/06 ,  H01L51/05

CPC classification number: H01L51/0048 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L51/0012 ,  H01L51/0541 ,  Y10S977/742 ,  Y10S977/842

Abstract: Embodiments of the present invention provide a method of forming carbon nanotube based semiconductor devices. The method includes creating a guiding structure in a substrate for forming a device; dispersing a plurality of carbon nanotubes inside the guiding structure, the plurality of carbon nanotubes having an orientation determined by the guiding structure; fixating the plurality of carbon nanotubes to the guiding structure; and forming one or more contacts to the device. Structure of the formed carbon nanotube device is also provided.

公开(公告)号：US09431523B2

公开(公告)日：2016-08-30

申请号：US14156489

申请日：2014-01-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/66818

Abstract: After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.

Abstract translation: 在半导体散热片上形成栅极结构之后，在形成凸起的有源区之前，使用定向离子束在半导体鳍片的端壁上形成与半导体鳍片的长度方向垂直的绝缘材料部分。 方向离子束的角度选择为包括半导体鳍片的长度方向的垂直平面，从而避免在半导体鳍片的纵向侧壁上形成电介质材料部分。 执行半导体材料的选择性外延以从半导体鳍片的侧壁表面生长凸起的有源区域。 可选地，可以在选择性外延工艺之前去除电介质材料部分的水平部分。 此外，可以在选择性外延工艺之后任选地去除电介质材料部分。

公开(公告)号：US20160218222A1

公开(公告)日：2016-07-28

申请号：US15089647

申请日：2016-04-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ramachandra Divakaruni ,  Arvind Kumar ,  Carl J. Radens

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7887 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/0234 ,  H01L21/306 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/11521 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7881

Abstract: A flash memory device in a dual fin single floating gate configuration is provided. Semiconductor fins are formed on a stack of a back gate conductor layer and a back gate dielectric layer. Pairs of semiconductor fins are formed in an array environment such that shallow trench isolation structures can be formed along the lengthwise direction of the semiconductor fins within the array. After formation of tunneling dielectrics on the sidewalls of the semiconductor fins, a floating gate electrode is formed between each pair of proximally located semiconductor fins by deposition of a conformal conductive material layer and an isotropic etch. A control gate dielectric and a control gate electrode are formed by deposition and patterning of a dielectric layer and a conductive material layer.