公开(公告)号：US09406803B2

公开(公告)日：2016-08-02

申请号：US14676239

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar ,  Steven Bentley

IPC: H01L21/326 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/161 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/18 ,  H01L29/161

Abstract: A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the substrate. A thermal process is performed to define a silicon alloy fin from the silicon alloy material and the fin and to define silicon alloy surface portions from the silicon alloy material and the exposed surface portions of the substrate. A semiconductor device includes a substrate, a fin defined on the substrate, the fin comprising a silicon alloy and having a substantially vertical sidewall, and silicon alloy surface portions on the substrate adjacent the fin.

Abstract translation: 一种方法包括在半导体衬底上形成至少一个翅片。 在所述散热片和所述基板的暴露的表面部分上形成硅合金材料。 执行热处理以从硅合金材料和翅片限定硅合金翅片，并且从硅合金材料和基底的暴露表面部分限定硅合金表面部分。 半导体器件包括衬底，限定在衬底上的鳍，鳍包括硅合金并且具有基本上垂直的侧壁，以及衬底上的与硅相邻的硅合金表面部分。

公开(公告)号：US09224865B2

公开(公告)日：2015-12-29

申请号：US13945627

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Ajey Poovannummoottil Jacob

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L29/66545 ,  H01L29/66795

Abstract: A FinFET has a structure including a semiconductor substrate, semiconductor fins and a gate spanning the fins. The fins each have a bottom region coupled to the substrate and a top active region. Between the bottom and top fin regions is a middle stack situated between a vertically elongated source and a vertically elongated drain. The stack includes a top channel region and a dielectric region immediately below the channel region, providing electrical isolation of the channel. The partial isolation structure can be used with both gate first and gate last fabrication processes.

Abstract translation: FinFET具有包括半导体衬底，半导体鳍片和横跨翅片的栅极的结构。 翅片各自具有连接到基底的底部区域和顶部活动区域。 位于底部和顶部翅片区域之间的是中间堆叠，位于垂直细长的源和垂直细长的排水管之间。 堆叠包括顶部通道区域和紧邻通道区域下方的电介质区域，提供通道的电隔离。 部分隔离结构可以与栅极第一和栅极末端制造工艺一起使用。

公开(公告)号：US20150021663A1

公开(公告)日：2015-01-22

申请号：US13945627

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Murat Kerem AKARVARDAR ,  Jody A. Fronheiser ,  Ajey Poovannummoottil JACOB

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L29/66545 ,  H01L29/66795

Abstract: A FinFET has a structure including a semiconductor substrate, semiconductor fins and a gate spanning the fins. The fins each have a bottom region coupled to the substrate and a top active region. Between the bottom and top fin regions is a middle stack situated between a vertically elongated source and a vertically elongated drain. The stack includes a top channel region and a dielectric region immediately below the channel region, providing electrical isolation of the channel. The partial isolation structure can be used with both gate first and gate last fabrication processes.

Abstract translation: FinFET具有包括半导体衬底，半导体鳍片和横跨翅片的栅极的结构。 翅片各自具有连接到基底的底部区域和顶部活动区域。 位于底部和顶部翅片区域之间的是中间堆叠，位于垂直细长的源和垂直细长的排水管之间。 堆叠包括顶部通道区域和紧邻通道区域下方的电介质区域，提供通道的电隔离。 部分隔离结构可以与栅极第一和栅极末端制造工艺一起使用。

公开(公告)号：US10170617B2

公开(公告)日：2019-01-01

申请号：US15424379

申请日：2017-02-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiseok Kim ,  Hiroaki Niimi ,  Hoon Kim ,  Puneet Harischandra Suvarna ,  Steven Bentley ,  Jody A. Fronheiser

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/36 ,  H01L29/66 ,  H01L29/417

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. The lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion.

公开(公告)号：US10170616B2

公开(公告)日：2019-01-01

申请号：US15268796

申请日：2016-09-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Steven J. Bentley ,  Jody A. Fronheiser

IPC: H01L21/337 ,  H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/40

Abstract: One illustrative method disclosed herein includes, among other things, defining a cavity in a plurality of layers of material positioned above a bottom source/drain (S/D) layer of semiconductor material, wherein a portion of the bottom source/drain (S/D) layer of semiconductor material is exposed at the bottom of the cavity, and performing at least one epi deposition process to form a vertically oriented channel semiconductor structure on the bottom source/drain (S/D) layer of semiconductor material and in the cavity and a top source/drain (S/D) layer of semiconductor material above the vertically oriented channel semiconductor structure. In this example, the method further includes removing at least one of the plurality of layers of material to thereby expose an outer perimeter surface of the vertically oriented channel semiconductor structure and forming a gate structure around the vertically oriented channel semiconductor structure.

公开(公告)号：US09508848B1

公开(公告)日：2016-11-29

申请号：US15012184

申请日：2016-02-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L21/324

CPC classification number: H01L21/324 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, removing at least a portion of a vertical height of portions of an overall fin structure that are not covered by a gate structure so as to result in the definition of a remaining portion of the overall fin structure that is positioned under the gate structure, wherein the remaining portion comprises a channel portion and a lower portion located under the channel portion. The method continues with the formation of a layer of heat-expandable material (HEM), performing a heating process on the HEM so as to cause the HEM to expand, recessing the HEM so as to expose edges of the channel portion and growing a semiconductor material above the HEM using the exposed edges of the channel portion as a growth surface.

Abstract translation: 本文公开的一种说明性方法包括除去未被栅极结构覆盖的整个鳍结构的部分的垂直高度的至少一部分，以便导致整个鳍的剩余部分的定义 所述结构位于所述栅极结构下方，其中所述剩​​余部分包括通道部分和位于所述通道部分下方的下部。 该方法继续形成一层可热膨胀材料（HEM），对HEM进行加热处理，以使HEM膨胀，使HEM凹陷，从而暴露通道部分的边缘并生长半导体 使用通道部分的暴露边缘作为生长表面的HEM上方的材料。

公开(公告)号：US09478663B2

公开(公告)日：2016-10-25

申请号：US14526617

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Yi Qi ,  Sylvie Mignot

IPC: H01L21/336 ,  H01L21/3205 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/18 ,  H01L29/165 ,  H01L21/02

CPC classification number: H01L29/7851 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/18 ,  H01L21/324 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842

Abstract: A method includes forming a fin on a semiconductor substrate and forming recesses on sidewalls of the fin. A silicon alloy material is formed in the recesses. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin. A semiconductor device includes a substrate, a fin defined on the substrate and an isolation structure disposed adjacent the fin. A first portion of the fin extending above the isolation structure has a substantially vertical sidewall and a different material composition than a second portion of the fin not extending above the isolation structure.

Abstract translation: 一种方法包括在半导体衬底上形成翅片并在翅片的侧壁上形成凹槽。 凹槽中形成硅合金材料。 进行热处理以从硅合金材料和翅片限定硅合金翅片部分。 半导体器件包括衬底，限定在衬底上的翅片和邻近翅片设置的隔离结构。 在隔离结构上方延伸的翅片的第一部分具有基本上垂直的侧壁和不同于在隔离结构上方延伸的翅片的第二部分的不同材料组成。

公开(公告)号：US20160190323A1

公开(公告)日：2016-06-30

申请号：US14676239

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar ,  Steven Bentley

IPC: H01L29/78 ,  H01L21/324 ,  H01L21/02 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/18 ,  H01L29/161

Abstract: A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the substrate. A thermal process is performed to define a silicon alloy fin from the silicon alloy material and the fin and to define silicon alloy surface portions from the silicon alloy material and the exposed surface portions of the substrate. A semiconductor device includes a substrate, a fin defined on the substrate, the fin comprising a silicon alloy and having a substantially vertical sidewall, and silicon alloy surface portions on the substrate adjacent the fin.

Abstract translation: 一种方法包括在半导体衬底上形成至少一个翅片。 在所述散热片和所述基板的暴露的表面部分上形成硅合金材料。 执行热处理以从硅合金材料和翅片限定硅合金翅片，并且从硅合金材料和基底的暴露表面部分限定硅合金表面部分。 半导体器件包括衬底，限定在衬底上的鳍，鳍包括硅合金并且具有基本上垂直的侧壁，以及衬底上的与硅相邻的硅合金表面部分。

公开(公告)号：US20160163863A1

公开(公告)日：2016-06-09

申请号：US14560361

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Witold P. Maszara ,  Jody A. Fronheiser

IPC: H01L29/78 ,  H01L29/201 ,  H01L21/02 ,  H01L29/161 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L29/7851 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/30604 ,  H01L21/32133 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/201 ,  H01L29/51 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785

Abstract: One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming an initial epi semiconductor cladding material around the exposed portion of a fin for an entire axial length of the fin, forming a sacrificial gate structure around a portion of the fin and the initial cladding material, removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove at least the exposed portion of the initial cladding material and thereby expose a surface of the fin within the replacement gate cavity, forming at least one replacement epi semiconductor cladding material around the exposed surface of the fin, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.

Abstract translation: 公开了在半导体器件的沟道区域中形成外延半导体包层材料的一种方法，其包括在翅片的整个轴向长度周围围绕翅片的暴露部分形成初始外延半导体包层材料，在其周围形成牺牲栅极结构 去除所述牺牲栅极结构从而限定替换栅极腔，通过所述替换栅极腔执行蚀刻工艺以移除所述初始包层材料的至少暴露部分，从而暴露出所述牺牲栅极结构 在替换栅极腔内的翅片的表面，在散热片的暴露表面周围形成至少一个替代外延半导体覆层材料，以及在所述替代栅极腔内形成围绕所述至少一个替代外延半导体包层材料的替代栅极结构。

公开(公告)号：US09362405B1

公开(公告)日：2016-06-07

申请号：US14560361

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Witold P. Maszara ,  Jody A. Fronheiser

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/161 ,  H01L29/201

CPC classification number: H01L29/7851 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/30604 ,  H01L21/32133 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/201 ,  H01L29/51 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785

Abstract: One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming an initial epi semiconductor cladding material around the exposed portion of a fin for an entire axial length of the fin, forming a sacrificial gate structure around a portion of the fin and the initial cladding material, removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove at least the exposed portion of the initial cladding material and thereby expose a surface of the fin within the replacement gate cavity, forming at least one replacement epi semiconductor cladding material around the exposed surface of the fin, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.

Abstract translation: 公开了在半导体器件的沟道区域中形成外延半导体包层材料的一种方法，其包括在翅片的整个轴向长度周围围绕翅片的暴露部分形成初始外延半导体包层材料，在其周围形成牺牲栅极结构 去除所述牺牲栅极结构从而限定替换栅极腔，通过所述替换栅极腔执行蚀刻工艺以移除所述初始包层材料的至少暴露部分，从而暴露出所述牺牲栅极结构 在替换栅极腔内的翅片的表面，在散热片的暴露表面周围形成至少一个替代外延半导体覆层材料，以及在所述替代栅极腔内形成围绕所述至少一个替代外延半导体包层材料的替代栅极结构。