公开(公告)号：US09570555B1

公开(公告)日：2017-02-14

申请号：US14926936

申请日：2015-10-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Balasubramanian Pranatharthiharan ,  Junli Wang ,  Ruilong Xie

IPC: H01L27/088 ,  H01L21/336 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/517 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/41791 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.

Abstract translation: 一种形成半导体器件的方法，包括提供具有第一间距的第一组翅片结构和具有第二间距的第二组翅片结构，其中所述第二间距大于所述第一间距。 在第一和第二组翅片结构上的外延半导体材料。 第一鳍结构上的外延半导体材料合并外延材料，第二鳍结构上的外延材料是非合并外延材料。 电介质衬垫形成在存在于第一和第二组鳍结构上的外延半导体材料的顶上。 电介质衬垫从存在于第二组鳍结构上的非合并外延材料的一部分去除。 桥接外延半导体材料形成在非合并外延材料的暴露表面上。

公开(公告)号：US20170040453A1

公开(公告)日：2017-02-09

申请号：US14817504

申请日：2015-08-04

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Rama Kambhampati ,  Junli Wang ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method for forming field effect transistors comprises forming a first dummy gate stack over a first fin, forming a second dummy gate stack over a second fin, depositing a first layer of spacer material on the first dummy gate stack, the first fin, the second dummy gate stack, and the second fin, patterning a first masking layer on the first dummy gate stack and the first fin, etching to remove portions of the first layer of spacer material and form a spacer adjacent to the second dummy gate stack, removing the first masking layer, epitaxially growing a silicon material on the second fin, depositing a layer of oxide material on the first layer of spacer material, the first epitaxial material and the second dummy gate stack, and depositing a second layer of spacer material on the layer of oxide material.

Abstract translation: 一种用于形成场效应晶体管的方法包括在第一鳍上形成第一虚拟栅极堆叠，在第二鳍片上形成第二虚拟栅极叠层，在第一伪栅极叠层上沉积第一层间隔物材料， 虚拟栅极堆叠和第二鳍片，在第一伪栅极堆叠和第一鳍片上构图第一掩模层，蚀刻以去除第一层间隔物材料的部分并形成邻近第二伪栅极叠层的间隔区， 第一掩模层，在所述第二鳍上外延生长硅材料，在所述第一隔离层材料层上沉积氧化物层，所述第一外延材料和所述第二伪栅极堆叠，以及在所述层上沉积第二隔离层材料层 的氧化物质。

公开(公告)号：US09548388B1

公开(公告)日：2017-01-17

申请号：US14817504

申请日：2015-08-04

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Rama Kambhampati ,  Junli Wang ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method for forming field effect transistors comprises forming a first dummy gate stack over a first fin, forming a second dummy gate stack over a second fin, depositing a first layer of spacer material on the first dummy gate stack, the first fin, the second dummy gate stack, and the second fin, patterning a first masking layer on the first dummy gate stack and the first fin, etching to remove portions of the first layer of spacer material and form a spacer adjacent to the second dummy gate stack, removing the first masking layer, epitaxially growing a silicon material on the second fin, depositing a layer of oxide material on the first layer of spacer material, the first epitaxial material and the second dummy gate stack, and depositing a second layer of spacer material on the layer of oxide material.

Abstract translation: 一种用于形成场效应晶体管的方法包括在第一鳍上形成第一虚拟栅极堆叠，在第二鳍片上形成第二虚拟栅极叠层，在第一伪栅极叠层上沉积第一层间隔物材料， 虚拟栅极堆叠和第二鳍片，在第一伪栅极堆叠和第一鳍片上构图第一掩模层，蚀刻以去除第一层间隔物材料的部分并形成邻近第二伪栅极叠层的间隔区， 第一掩模层，在所述第二鳍上外延生长硅材料，在所述第一隔离层材料层上沉积氧化物层，所述第一外延材料和所述第二伪栅极堆叠，以及在所述层上沉积第二隔离层材料层 的氧化物质。

公开(公告)号：US10090202B2

公开(公告)日：2018-10-02

申请号：US15357287

申请日：2016-11-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Balasubramanian Pranatharthiharan ,  Junli Wang ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06

Abstract: A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.

公开(公告)号：US20180197980A1

公开(公告)日：2018-07-12

申请号：US15913194

申请日：2018-03-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hong He ,  Chiahsun Tseng ,  Junli Wang ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/785 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

Abstract: A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.

公开(公告)号：US20170365682A1

公开(公告)日：2017-12-21

申请号：US15689565

申请日：2017-08-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Balasubramanian Pranatharthiharan ,  Junli Wang ,  Ruilong Xie

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L21/823418 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/41791 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.

公开(公告)号：US20170125299A1

公开(公告)日：2017-05-04

申请号：US15357287

申请日：2016-11-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Balasubramanian Pranatharthiharan ,  Junli Wang ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/517 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/41791 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.

公开(公告)号：US09634010B2

公开(公告)日：2017-04-25

申请号：US15168725

申请日：2016-05-31

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Rama Kambhampati ,  Junli Wang ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method for forming field effect transistors comprises forming a first dummy gate stack over a first fin, forming a second dummy gate stack over a second fin, depositing a first layer of spacer material on the first dummy gate stack, the first fin, the second dummy gate stack, and the second fin, patterning a first masking layer on the first dummy gate stack and the first fin, etching to remove portions of the first layer of spacer material and form a spacer adjacent to the second dummy gate stack, removing the first masking layer, epitaxially growing a silicon material on the second fin, depositing a layer of oxide material on the first layer of spacer material, the first epitaxial material and the second dummy gate stack, and depositing a second layer of spacer material on the layer of oxide material.

公开(公告)号：US20170040224A1

公开(公告)日：2017-02-09

申请号：US15252586

申请日：2016-08-31

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Rama Kambhampati ,  Junli Wang ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method for forming field effect transistors comprises forming a first dummy gate stack over a first fin, forming a second dummy gate stack over a second fin, depositing a first layer of spacer material on the first dummy gate stack, the first fin, the second dummy gate stack, and the second fin, patterning a first masking layer on the first dummy gate stack and the first fin, etching to remove portions of the first layer of spacer material and form a spacer adjacent to the second dummy gate stack, removing the first masking layer, epitaxially growing a silicon material on the second fin, depositing a layer of oxide material on the first layer of spacer material, the first epitaxial material and the second dummy gate stack, and depositing a second layer of spacer material on the layer of oxide material.

Abstract translation: 一种用于形成场效应晶体管的方法包括在第一鳍上形成第一虚拟栅极堆叠，在第二鳍片上形成第二虚拟栅极叠层，在第一伪栅极叠层上沉积第一层间隔物材料， 虚拟栅极堆叠和第二鳍片，在第一伪栅极堆叠和第一鳍片上构图第一掩模层，蚀刻以去除第一层间隔物材料的部分并形成邻近第二伪栅极叠层的间隔区， 第一掩模层，在所述第二鳍上外延生长硅材料，在所述第一隔离层材料层上沉积氧化物层，所述第一外延材料和所述第二伪栅极堆叠，以及在所述层上沉积第二隔离层材料层 的氧化物质。

公开(公告)号：US09472670B1

公开(公告)日：2016-10-18

申请号：US15085376

申请日：2016-03-30

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Rama Kambhampati ,  Junli Wang ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method for forming field effect transistors comprises forming a first dummy gate stack over a first fin, forming a second dummy gate stack over a second fin, depositing a first layer of spacer material on the first dummy gate stack, the first fin, the second dummy gate stack, and the second fin, patterning a first masking layer on the first dummy gate stack and the first fin, etching to remove portions of the first layer of spacer material and form a spacer adjacent to the second dummy gate stack, removing the first masking layer, epitaxially growing a silicon material on the second fin, depositing a layer of oxide material on the first layer of spacer material, the first epitaxial material and the second dummy gate stack, and depositing a second layer of spacer material on the layer of oxide material.

Abstract translation: 一种用于形成场效应晶体管的方法包括在第一鳍上形成第一虚拟栅极堆叠，在第二鳍片上形成第二虚拟栅极叠层，在第一伪栅极叠层上沉积第一层间隔物材料， 虚拟栅极堆叠和第二鳍片，在第一伪栅极堆叠和第一鳍片上构图第一掩模层，蚀刻以去除第一层间隔物材料的部分并形成邻近第二伪栅极叠层的间隔区， 第一掩模层，在所述第二鳍上外延生长硅材料，在所述第一隔离层材料层上沉积氧化物层，所述第一外延材料和所述第二伪栅极堆叠，以及在所述层上沉积第二隔离层材料层 的氧化物质。