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    Borderless contact formation through metal-recess dual cap integration
    12.
    发明授权
    Borderless contact formation through metal-recess dual cap integration 有权
    无边界接触形成通过金属凹槽双盖整合

    公开(公告)号：US09502528B2

    公开(公告)日：2016-11-22

    申请号：US14469014

    申请日：2014-08-26

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guillaume Bouche ,  Jason E. Stephens ,  Tuhin Guha Neogi ,  Mark A. Zaleski ,  Andy Chih-Hung Wei

    IPC: H01L29/66 ,  H01L29/417 ,  H01L29/165 ,  H01L21/8238 ,  H01L27/092

    CPC classification number: H01L29/66545 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6653

    Abstract: An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A first block mask is formed over a portion of the semiconductor structure. This first block mask covers at least a portion of at least one source/drain (s/d) contact location. An s/d capping layer is formed over the s/d contact locations that are not covered by the first block mask. This s/d capping layer is comprised of a first capping substance. Then, a second block mask is formed over the semiconductor structure. This second block mask exposes at least one gate location. A gate capping layer, which comprises a second capping substance, is removed from the exposed gate location(s). Then a metal contact layer is deposited, which forms a contact to both the s/d contact location(s) and the gate contact location(s).

    Abstract translation: 提供了一种在半导体结构中提供改进的晶体管触点的改进的半导体结构和制造方法。 在半导体结构的一部分上形成第一块掩模。 该第一块掩模覆盖至少一个源/漏（s / d）接触位置的至少一部分。 在未被第一块掩模覆盖的s / d接触位置上形成s / d覆盖层。 该s / d封盖层由第一封盖物质构成。 然后，在半导体结构上形成第二块掩模。 该第二块掩模暴露至少一个门位置。 包括第二封盖物质的栅极覆盖层从暴露的栅极位置移除。 然后沉积金属接触层，其形成与s / d接触位置和栅极接触位置的接触。

    Precut metal lines
    16.
    发明授权
    Precut metal lines 有权
    预切金属线

    公开(公告)号：US09263325B1

    公开(公告)日：2016-02-16

    申请号：US14463801

    申请日：2014-08-20

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Mark A. Zaleski

    IPC: H01L21/30 ,  H01L21/46 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/285 ,  H01L23/532

    CPC classification number: H01L23/5226 ,  H01L21/32139 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Embodiments of the present invention provide a method for cuts of sacrificial metal lines in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. A line cut lithography stack is deposited and patterned over the sacrificial Mx+1 lines and a cut cavity is formed. The cut cavity is filled with dielectric material. A selective etch process removes the sacrificial Mx+1 lines, preserving the dielectric that fills in the cut cavity. Precut metal lines are then formed by depositing metal where the sacrificial Mx+1 lines were removed. Thus embodiments of the present invention provide precut metal lines, and do not require metal cutting. By avoiding the need for metal cutting, the risks associated with metal cutting are avoided.

    Abstract translation: 本发明的实施例提供了一种在线结构后端切割牺牲金属线的方法。 牺牲Mx + 1线形成在金属Mx线之上。 在牺牲Mx + 1线上沉积并图案化切割光刻叠层并形成切割腔。 切割腔填充有介电材料。 选择性蚀刻工艺去除牺牲Mx + 1线，保留填充切割腔的电介质。 然后通过沉积除去牺牲Mx + 1线的金属形成预切割的金属线。 因此，本发明的实施例提供预切割金属线，并且不需要金属切割。 通过避免金属切割的需要，避免与金属切割相关的风险。

    SELF-ALIGNED VIA AND AIR GAP
    19.
    发明申请
    SELF-ALIGNED VIA AND AIR GAP 有权
    自对准通风和空气隙

    公开(公告)号：US20160260666A1

    公开(公告)日：2016-09-08

    申请号：US15155569

    申请日：2016-05-16

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Andy Chih-Hung Wei ,  Mark A. Zaleski

    IPC: H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L23/532

    CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/5329 ,  H01L29/0649

    Abstract: Provided are approaches for forming a self-aligned via and an air gap within a semiconductor device. Specifically, one approach produces a device having: a first metal line beneath a second metal line within an ultra low-k (ULK) dielectric, the first metal line connected to the second metal line by a first via; a dielectric capping layer formed over the second metal line; a third metal line within first and second via openings formed within a ULK fill material formed over the dielectric capping layer, wherein the third metal line within the first via opening extends to a top surface of the dielectric capping layer, and wherein the third metal line within the second via opening is connected to the second metal by a second via passing through the dielectric capping layer; and an air gap formed between the third metal line within the first and seconds via openings.

    Abstract translation: 提供了用于在半导体器件内形成自对准通孔和气隙的方法。 具体地，一种方法产生一种器件，其具有：在超低k（ULK）电介质中的第二金属线下方的第一金属线，所述第一金属线通过第一通孔连接到所述第二金属线; 形成在所述第二金属线上的电介质覆盖层; 形成在形成在电介质覆盖层上的ULK填充材料内的第一和第二通孔内的第三金属线，其中第一通孔开口内的第三金属线延伸到介电覆盖层的顶表面，并且其中第三金属线 在第二通孔开口内通过穿过电介质盖层的第二通孔连接到第二金属; 以及形成在第一和第二通孔之间的第三金属线之间的气隙。

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