公开(公告)号：US10170617B2

公开(公告)日：2019-01-01

申请号：US15424379

申请日：2017-02-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiseok Kim ,  Hiroaki Niimi ,  Hoon Kim ,  Puneet Harischandra Suvarna ,  Steven Bentley ,  Jody A. Fronheiser

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/36 ,  H01L29/66 ,  H01L29/417

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. The lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion.

公开(公告)号：US09947789B1

公开(公告)日：2018-04-17

申请号：US15295338

申请日：2016-10-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Puneet Harischandra Suvarna

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/786 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/78696

Abstract: A vertical transistor includes a semiconductor substrate, and fin(s) over the semiconductor substrate (n-type fin(s) and/or p-type fin(s)), the fin(s) acting as vertical transistor channels for vertical transistors. Each of the fin(s) is lattice mismatched at one or more interface(s), being stressed from below, from above, from fin sidewalls or combination(s) thereof. The vertical transistors can be realized by providing a semiconductor substrate, forming stressed fin(s) of vertical transistor(s) acting as vertical transistor channels, the stressed fin(s) being lattice mismatched at one or more interfaces and being stressed from below, above, sidewalls or combination(s) thereof.

公开(公告)号：US20180083121A1

公开(公告)日：2018-03-22

申请号：US15268751

申请日：2016-09-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Puneet Harischandra Suvarna ,  Steven J. Bentley ,  Daniel Chanemougame

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/306 ,  H01L29/423

CPC classification number: H01L29/66666 ,  H01L29/0847 ,  H01L29/165

Abstract: One illustrative method disclosed herein includes, among other things, forming a vertically oriented channel semiconductor structure above a substrate, performing an epi deposition process to simultaneously form at least a portion of a bottom source/drain region and at least a portion of a top source/drain region during the epi deposition process and, after performing the epi deposition process, forming a gate structure around a portion of the vertically oriented channel semiconductor structure.

公开(公告)号：US10784171B2

公开(公告)日：2020-09-22

申请号：US16577032

申请日：2019-09-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Puneet Harischandra Suvarna

IPC: H01L21/84 ,  H01L27/12 ,  H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

Abstract: A device is disclosed that includes a first transistor device of a first type and a second transistor device of a second type positioned vertically above the first transistor, wherein the first type and second type of transistors are opposite types. The device also includes a gate structure for the first transistor and the second transistor, wherein the gate structure comprises a first gate electrode for the first transistor and a second gate electrode for the second transistor and a gate stack spacer positioned vertically between the first gate electrode and the second gate electrode so as to electrically isolate the first gate electrode from the second gate electrode.

公开(公告)号：US10510622B1

公开(公告)日：2019-12-17

申请号：US16047456

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Puneet Harischandra Suvarna

IPC: H01L21/84 ,  H01L27/12 ,  H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

Abstract: A method includes forming a stack of semiconductor material layers. A first spacer is formed adjacent a lower region at a first end of the stack, and a second spacer is formed adjacent an upper region positioned at a second end of the stack. A gate structure and sidewall spacer are formed above the stack. The gate structure and a first subset of the semiconductor layers are removed to define inner cavities and a gate cavity. A gate insulation layer is formed. A first conductive material is formed in the inner cavities. The first conductive material is selectively removed from the inner cavities in the upper region. The first conductive material in the inner cavities in the lower region remains as a first gate electrode. A second conductive material is formed in the inner cavities in the upper region to define a second gate electrode.

公开(公告)号：US10418449B2

公开(公告)日：2019-09-17

申请号：US15866855

申请日：2018-01-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bipul C. Paul ,  Ruilong Xie ,  Puneet Harischandra Suvarna

IPC: H01L21/70 ,  H01L29/417 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/48

Abstract: Structures and circuits including multiple nanosheet field-effect transistors and methods of forming such structures and circuits. A complementary field-effect transistor includes a first nanosheet transistor with a source/drain region and a second nanosheet transistor with a source/drain region stacked over the source/drain region of the first nanosheet transistor. A contact extends vertically to connect the source/drain region of the first nanosheet transistor of the complementary field-effect transistor and the source/drain region of the second nanosheet transistor of the complementary field-effect transistor.

公开(公告)号：US20190115444A1

公开(公告)日：2019-04-18

申请号：US15783270

申请日：2017-10-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven BENTLEY ,  Rohit GALATAGE ,  Puneet Harischandra Suvarna

IPC: H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L23/535 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/516 ,  H01L21/28079 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/535 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A layer of ferroelectric material is incorporated into the gate contact of a metal oxide semiconductor field effect transistor (MOSFET), i.e., outside of the device active area. Flexibility in the deposition and patterning of the ferroelectric layer geometry allows for efficient matching between the capacitance of the ferroelectric layer and the capacitance of the gate, providing a step-up voltage transformer, decreased threshold voltage, and a sub-threshold swing for the device of less than 60 mV/decade.

公开(公告)号：US10141414B1

公开(公告)日：2018-11-27

申请号：US15784500

申请日：2017-10-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rohit Galatage ,  Steven Bentley ,  Puneet Harischandra Suvarna ,  Zoran Krivokapic

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/78

Abstract: A gate electrode structure of a transistor element may be provided as a series connection of a negative capacitor portion and a floating electrode portion. When forming the negative capacitor portion, the value of the negative capacitance may be adjusted on the basis of two different mechanisms or manufacturing processes, thereby providing superior matching of the positive floating gate electrode portion and the negative capacitor portion. For example, the layer thickness of the ferroelectric material and the effective capacitive area of the dielectric material may be adjusted on the basis of independent manufacturing processes.