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公开(公告)号:US09257391B2
公开(公告)日:2016-02-09
申请号:US13873356
申请日:2013-04-30
Applicant: GLOBALFOUNDRIES INC.
Inventor: Junjing Bao , Griselda Bonilla , Samuel S. Choi , Ronald G. Filippi , Naftali E. Lustig , Andrew H. Simon
IPC: H01L21/4763 , H01L21/44 , H01L23/532 , H01L23/528 , B82Y40/00 , B82Y30/00 , H01L21/768
CPC classification number: H01L23/53276 , B82Y30/00 , B82Y40/00 , H01L21/76831 , H01L21/76838 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L2924/0002 , Y10S977/734 , Y10S977/842 , Y10S977/932 , H01L2924/00
Abstract: Hybrid metal-graphene interconnect structures and methods of forming the same. The structure may include a first end metal, a second end metal, a conductive line including one or more graphene portions extending from the first end metal to the second end metal, and one or more line barrier layers partially surrounding each of the one or more graphene portions. The conductive line may further include one or more intermediate metals separating each of the one or more graphene portions. Methods of forming said interconnect structures may include forming a plurality of metals including a first end metal and a second end metal in a dielectric layer, forming one or more line trenches between each of the plurality of metals, forming a line barrier layer in each of the one or more line trenches, and filling the one or more line trenches with graphene.
Abstract translation: 混合金属 - 石墨烯互连结构及其形成方法。 该结构可以包括第一端金属,第二端金属,包括从第一端金属延伸到第二端金属的一个或多个石墨烯部分的导电线,以及一个或多个部分围绕一个或多个 石墨烯部分。 导电线还可以包括分离一个或多个石墨烯部分中的每一个的一个或多个中间金属。 形成所述互连结构的方法可以包括在电介质层中形成包括第一端金属和第二端金属的多种金属,在多个金属中的每一个之间形成一个或多个管线沟槽,在每一个中形成线路阻挡层 一个或多个线沟槽,并用石墨烯填充一个或多个线沟槽。
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公开(公告)号:US10103068B2
公开(公告)日:2018-10-16
申请号:US14743208
申请日:2015-06-18
Applicant: GLOBALFOUNDRIES INC.
Inventor: Griselda Bonilla , Samuel S. S. Choi , Ronald G. Filippi , Elbert E. Huang , Naftali E. Lustig , Andrew H. Simon
Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure includes a wiring line and a via upon and electrically contacting the wiring line. The via induces lateral etching voids between the via and the wiring line below the via upon the surface of the wiring line. The second circuit structure includes a similar wiring line, relative to the reference wiring line, without or fewer via thereupon. The first circuit structure is therefore relatively more prone to lateral etching void formation as compared to the second circuit structure. Resistances are measured across the first circuit structure and the second circuit structure and compared against a comparison threshold to determine whether the first circuit structure includes one or more lateral etching voids. If the first structure is deemed to not include lateral etching voids, the fabrication process of the device may be deemed reliable.
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公开(公告)号:US09536842B2
公开(公告)日:2017-01-03
申请号:US14574430
申请日:2014-12-18
Applicant: GLOBALFOUNDRIES INC.
Inventor: Junjing Bao , Griselda Bonilla , Samuel S. Choi , Ronald G. Filippi , Xiao H. Liu , Naftali E. Lustig , Andrew H. Simon
IPC: H01L23/00 , H01L23/48 , H01L21/768
CPC classification number: H01L23/562 , H01L21/7682 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
Abstract: An method including forming multiple interconnect levels on top of one another, each level comprising a metal interconnect and a crack stop both embedded in a dielectric layer, and a dielectric capping layer directly on top of the dielectric layer and directly on top of the metal interconnect, the crack stop is an air gap which intersects an interface between the dielectric layer and the dielectric capping layer of each interconnect level, and forming a through substrate via through the multiple interconnect levels adjacent to, but not in direct contact with, the crack stop, the crack stop of each interconnect level is directly between the metal interconnect of each interconnect level and the through substrate via to prevent cracks caused during fabrication from propagating away from the through substrate via and damaging the metal interconnect.
Abstract translation: 一种包括在彼此之上形成多个互连层的方法,每个层包括金属互连和嵌入在电介质层中的裂纹阻挡层,以及直接位于介电层顶部并且直接位于金属互连顶部的电介质覆盖层 裂缝停止是与每个互连层的电介质层和电介质覆盖层之间的界面相交的气隙,并且通过与裂纹停止相邻但不直接接触的多个互连层形成通孔基板通孔 每个互连级别的裂纹停止点直接位于每个互连级别的金属互连和贯通基板通孔之间,以防止制造过程中产生的裂纹从穿过基板传播并损坏金属互连。
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公开(公告)号:US09431346B2
公开(公告)日:2016-08-30
申请号:US14454765
申请日:2014-08-08
Applicant: GLOBALFOUNDRIES INC.
Inventor: Junjing Bao , Griselda Bonilla , Samuel S. Choi , Ronald G. Filippi , Andrew T. Kim , Naftali E. Lustig , Andrew H. Simon
IPC: H01L21/47 , H01L21/44 , H01L23/532 , H01L23/525 , B82Y40/00 , B82Y30/00
CPC classification number: H01L23/53276 , B82Y30/00 , B82Y40/00 , H01L23/5256 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L2924/0002 , Y10S977/734 , Y10S977/794 , Y10S977/842 , Y10S977/932 , H01L2924/00
Abstract: A structure including an Mx level including a first Mx metal, a second Mx metal, and a third Mx metal abutting and electrically connected in sequence with one another, the second Mx metal including graphene, and an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal and a via, the via electrically connects the third Mx metal to the Mx+1 metal in a vertical orientation.
Abstract translation: 包括Mx级的结构,所述Mx级包括彼此顺序地邻接和电连接的第一Mx金属,第二Mx金属和第三Mx金属,所述第二Mx金属包括石墨烯,以及Mx级以上的Mx + 1级, Mx + 1电平包括Mx + 1金属和通孔,通孔以垂直方向将第三Mx金属电连接到Mx + 1金属。
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15.
公开(公告)号:US09431292B1
公开(公告)日:2016-08-30
申请号:US14698948
申请日:2015-04-29
Applicant: GLOBALFOUNDRIES INC.
Inventor: Griselda Bonilla , Samuel S. S. Choi , Ronald G. Filippi , Elbert E. Huang , Naftali E. Lustig , Andrew H. Simon
IPC: H01L21/4763 , H01L21/768 , H01L23/532
CPC classification number: H01L21/76808 , H01L21/76802 , H01L21/76831 , H01L21/76835 , H01L21/76844 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L23/53238 , H01L23/53295 , H01L2221/1036
Abstract: After forming at least one opening in a material stack comprising a sacrificial metal template layer overlying a first dielectric material layer, a sacrificial material portion is deposited in the at least one opening as a place holder for an interconnect structure later formed. Next, the sacrificial metal template layer is removed and a second dielectric material layer is formed to fill voids that were previously occupied by the sacrificial metal template layer. After removing the sacrificial material portion from the at least one opening, an interconnect structure is formed within the at least one opening.
Abstract translation: 在包括覆盖在第一介电材料层上的牺牲金属模板层的材料堆叠中形成至少一个开口之后,牺牲材料部分沉积在所述至少一个开口中,作为稍后形成的互连结构的占位符。 接下来,去除牺牲金属模板层,并且形成第二介电材料层以填充先前被牺牲金属模板层占据的空隙。 在从至少一个开口去除牺牲材料部分之后,在至少一个开口内形成互连结构。
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公开(公告)号:US20160181208A1
公开(公告)日:2016-06-23
申请号:US14574430
申请日:2014-12-18
Applicant: GLOBALFOUNDRIES INC.
Inventor: Junjing Bao , Griselda Bonilla , Samuel S. Choi , Ronald G. Filippi , Xiao H. Liu , Naftali E. Lustig , Andrew H. Simon
IPC: H01L23/00 , H01L23/48 , H01L21/768
CPC classification number: H01L23/562 , H01L21/7682 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
Abstract: An method including forming multiple interconnect levels on top of one another, each level comprising a metal interconnect and a crack stop both embedded in a dielectric layer, and a dielectric capping layer directly on top of the dielectric layer and directly on top of the metal interconnect, the crack stop is an air gap which intersects an interface between the dielectric layer and the dielectric capping layer of each interconnect level, and forming a through substrate via through the multiple interconnect levels adjacent to, but not in direct contact with, the crack stop, the crack stop of each interconnect level is directly between the metal interconnect of each interconnect level and the through substrate via to prevent cracks caused during fabrication from propagating away from the through substrate via and damaging the metal interconnect.
Abstract translation: 一种包括在彼此之上形成多个互连层的方法,每个层包括金属互连和嵌入在电介质层中的裂纹阻挡层,以及直接位于介电层顶部并且直接位于金属互连顶部的电介质覆盖层 裂缝停止是与每个互连层的电介质层和电介质覆盖层之间的界面相交的气隙,并且通过与裂纹停止相邻但不直接接触的多个互连层形成通孔基板通孔 每个互连级别的裂纹停止点直接位于每个互连级别的金属互连和贯通基板通孔之间,以防止制造过程中产生的裂纹从穿过基板传播并损坏金属互连。
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17.
公开(公告)号:US09443776B2
公开(公告)日:2016-09-13
申请号:US14729446
申请日:2015-06-03
Applicant: GLOBALFOUNDRIES INC.
Inventor: Ronald G. Filippi , Jason P. Gill , Vincent J. McGahay , Paul S. McLaughlin , Conal E. Murray , Hazara S. Rathore , Thomas M. Shaw , Ping-Chuan Wang
IPC: H01L23/00 , H01L21/66 , H01L23/522 , H05K1/09 , H05K1/02
CPC classification number: H01L22/34 , H01L22/32 , H01L23/5226 , H01L23/562 , H01L2924/0002 , H05K1/0268 , H05K1/0269 , H05K1/092 , Y10S438/927 , Y10T29/49004 , H01L2924/00
Abstract: A test structure used to determine reliability performance includes a patterned metallization structure having multiple interfaces, which provide stress risers. A dielectric material surrounds the metallization structure, where a mismatch in coefficients of thermal expansion (CTE) between the metallization structure and the surrounding dielectric material exist such that a thermal strain value is provided to cause failures under given stress conditions as a result of CTE mismatch to provide a yield indicative of reliability for a manufacturing design.
Abstract translation: 用于确定可靠性性能的测试结构包括具有多个界面的图案化金属化结构,其提供应力梯度。 电介质材料围绕金属化结构,其中存在金属化结构和周围电介质材料之间的热膨胀系数(CTE)不匹配,使得提供热应变值以引起由于CTE失配导致的给定应力条件下的故障 以提供指示制造设计的可靠性的产量。
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