公开(公告)号：US09435852B1

公开(公告)日：2016-09-06

申请号：US14862587

申请日：2015-09-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andrew T. Kim ,  Cathryn J. Christiansen ,  Ping-Chuan Wang

IPC: H01L23/48 ,  G01R31/28 ,  H01L23/528 ,  H01L23/522 ,  H01L21/66

CPC classification number: G01R31/2884 ,  H01L22/34

Abstract: Aspects of the present disclosure provide an integrated circuit (IC) test structure. An IC structure according to the present disclosure can include: a monitor chain having a first end electrically connected to a second end through a plurality of metal wires each positioned within one of a first metal level and a second metal level, wherein the first metal level is vertically separated from the second metal level; a first test wire positioned within the first metal level and extending in a first direction, wherein the first test wire is electrically insulated from the monitor chain; and a second test wire positioned within the second metal level and extending in a second direction, wherein the second test wire is electrically insulated from the monitor chain and the first test wire, and wherein the first direction is different from the second direction.

Abstract translation: 本公开的方面提供了集成电路（IC）测试结构。 根据本公开的IC结构可以包括：监视器链，其具有通过多个金属线电连接到第二端的第一端，每条金属线位于第一金属层和第二金属层之一内，其中第一金属层 与第二金属层垂直分离; 第一测试线定位在第一金属水平面内并沿第一方向延伸，其中第一测试线与监视器链电绝缘; 以及第二测试线，其位于所述第二金属层内并且在第二方向上延伸，其中所述第二测试线与所述监视器链和所述第一测试线电绝缘，并且其中所述第一方向与所述第二方向不同。

公开(公告)号：US09817063B2

公开(公告)日：2017-11-14

申请号：US15048704

申请日：2016-02-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ping-Chuan Wang ,  Andrew T. Kim ,  Ronald G. Filippi

IPC: G01R31/28 ,  H01L21/66 ,  H01L23/522 ,  H01L27/08

CPC classification number: G01R31/2858 ,  H01L22/34 ,  H01L23/5226 ,  H01L27/0802

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interconnect reliability structures and methods of manufacture. The structure includes: a plurality of resistors; and a voltmeter configured to sense a relative difference in resistance of the plurality of resistors indicative of at least one of a via-depletion and line-depletion.

公开(公告)号：US09478509B2

公开(公告)日：2016-10-25

申请号：US14198711

申请日：2014-03-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Andrew T. Kim ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L23/481 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/03426 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/039 ,  H01L2224/0391 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05015 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/08145 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/1317 ,  H01L2224/13171 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2924/00014 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2224/034

Abstract: The present invention relates generally to flip chip technology and more particularly, to a method and structure for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure. In an embodiment, a method is disclosed that may include forming a bonding pad having one or more anchor regions that extend into a semiconductor structure and may inhibit the bonding pad from physically separating from the TSV during temperature fluctuations.

Abstract translation: 本发明一般涉及倒装芯片技术，更具体地说，涉及用于在半导体结构上制造机械锚定的控制崩溃芯片连接（C 4）焊盘的方法和结构。 在一个实施例中，公开了一种方法，其可以包括形成具有延伸到半导体结构中的一个或多个锚定区域的焊盘，并且可能在温度波动期间阻止焊盘与TSV物理分离。

公开(公告)号：US09431346B2

公开(公告)日：2016-08-30

申请号：US14454765

申请日：2014-08-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  Ronald G. Filippi ,  Andrew T. Kim ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L21/47 ,  H01L21/44 ,  H01L23/532 ,  H01L23/525 ,  B82Y40/00 ,  B82Y30/00

CPC classification number: H01L23/53276 ,  B82Y30/00 ,  B82Y40/00 ,  H01L23/5256 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  Y10S977/734 ,  Y10S977/794 ,  Y10S977/842 ,  Y10S977/932 ,  H01L2924/00

Abstract: A structure including an Mx level including a first Mx metal, a second Mx metal, and a third Mx metal abutting and electrically connected in sequence with one another, the second Mx metal including graphene, and an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal and a via, the via electrically connects the third Mx metal to the Mx+1 metal in a vertical orientation.

Abstract translation: 包括Mx级的结构，所述Mx级包括彼此顺序地邻接和电连接的第一Mx金属，第二Mx金属和第三Mx金属，所述第二Mx金属包括石墨烯，以及Mx级以上的Mx + 1级， Mx + 1电平包括Mx + 1金属和通孔，通孔以垂直方向将第三Mx金属电连接到Mx + 1金属。

公开(公告)号：US10325862B2

公开(公告)日：2019-06-18

申请号：US15657666

申请日：2017-07-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Andrew T. Kim ,  Ping-Chuan Wang

IPC: H01L21/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48

Abstract: Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.

公开(公告)号：US20170242067A1

公开(公告)日：2017-08-24

申请号：US15048704

申请日：2016-02-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ping-Chuan Wang ,  Andrew T. Kim ,  Ronald G. Filippi

IPC: G01R31/28 ,  H01L23/522 ,  H01L27/08 ,  H01L21/66

CPC classification number: G01R31/2858 ,  H01L22/34 ,  H01L23/5226 ,  H01L27/0802

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interconnect reliability structures and methods of manufacture. The structure includes: a plurality of resistors; and a voltmeter configured to sense a relative difference in resistance of the plurality of resistors indicative of at least one of a via-depletion and line-depletion.

公开(公告)号：US09318413B2

公开(公告)日：2016-04-19

申请号：US14065451

申请日：2013-10-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Fen Chen ,  Andrew T. Kim ,  Minhua Lu ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/481 ,  H01L21/76849 ,  H01L21/76898 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure generally provides for an integrated circuit (IC) structure with a TSV, and methods of manufacturing the IC structure and the TSV. An IC structure according to embodiments of the present invention may include a through-semiconductor via (TSV) embedded within a substrate, the TSV having an axial end; and a metal cap contacting the axial end of the TSV, wherein the metal cap has a greater electrical resistivity than the TSV.

Abstract translation: 本公开通常提供具有TSV的集成电路（IC）结构以及制造IC结构和TSV的方法。 根据本发明的实施例的IC结构可以包括嵌入在基板内的贯穿半导体通孔（TSV），TSV具有轴向端; 以及与TSV的轴向端接触的金属盖，其中金属帽具有比TSV更大的电阻率。