公开(公告)号：US09865704B2

公开(公告)日：2018-01-09

申请号：US15168690

申请日：2016-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Kwan-Yong Lim ,  Min Gyu Sung ,  Ryan Ryoung-Han Kim

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: One illustrative integrated circuit product disclosed herein includes, among other things, a plurality of FinFET devices, each of which comprises a gate structure comprising a high-k gate insulation material and at least one layer of metal, a single diffusion break (SDB) isolation structure positioned in a first trench defined in a semiconductor substrate between first and second active regions, the SDB isolation structure comprising the high-k insulating material and the at least one layer of metal, and a double diffusion break (DDB) isolation structure positioned in a second trench defined in a semiconductor substrate between third and fourth active regions, the DDB isolation structure comprising a first insulating material that substantially fills the second trench.

公开(公告)号：US09553028B2

公开(公告)日：2017-01-24

申请号：US14219365

申请日：2014-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Ryan Ryoung-Han Kim

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L23/485 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/823475 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/53228 ,  H01L23/53257 ,  H01L27/088 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a layer of insulating material above first and second transistors, within the layer of insulating material, forming a set of initial device-level contacts for each of the first and second transistors, wherein each set of initial device-level contacts comprises a plurality of source/drain contacts and a gate contact, forming an initial local interconnect structure that is conductively coupled to one of the initial device-level contacts in each of the first and second transistors, and removing the initial local interconnect structure and portions, but not all, of the initial device-level contacts for each the first and second transistors. The method also includes forming a copper local interconnect structure and copper caps above the recessed device-level contacts.

Abstract translation: 一种方法包括在绝缘材料层内的第一和第二晶体管之上形成绝缘材料层，形成用于第一和第二晶体管中的每一个的一组初始器件级触点，其中每组初始器件级触点包括 多个源极/漏极触点和栅极接触，形成初始局部互连结构，其导电耦合到第一和第二晶体管中的每一个中的初始器件级触点之一，以及去除初始局部互连结构和部分， 但不是所有的第一和第二晶体管的初始器件级触点。 该方法还包括在凹入的器件级触点上方形成铜局部互连结构和铜帽。

公开(公告)号：US09412616B1

公开(公告)日：2016-08-09

申请号：US14942448

申请日：2015-11-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Kwan-Yong Lim ,  Min Gyu Sung ,  Ryan Ryoung-Han Kim

IPC: H01L21/00 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/283 ,  H01L21/762

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: One illustrative method disclosed herein includes, among other things, forming a multi-layer patterned masking layer comprised of first and second layers of material and first and second openings that extend through both of the first and second layers of material, wherein the first opening is positioned above a first area of the substrate where the DDB isolation structure will be formed and the second opening is positioned above a second area of the substrate where the SDB isolation structure will be formed. The method also includes performing a first process operation through the first opening to form the DDB isolation structure, performing a second process operation to remove the second layer of material and to expose the first opening in the first layer of material, and performing a third process operation through the second opening to form the SDB isolation structure.

Abstract translation: 本文公开的一种说明性方法包括形成由第一和第二层材料构成的多层图案化掩模层，以及延伸穿过第一和第二材料层的第一和第二开口，其中第一开口是 位于基板的将形成DDB隔离结构的第一区域之上，并且第二开口位于衬底的将形成SDB隔离结构的第二区域之上。 该方法还包括通过第一开口执行第一处理操作以形成DDB隔离结构，执行第二处理操作以去除第二层材料并露出第一层材料中的第一开口，以及执行第三工艺 通过第二次开启操作形成SDB隔离结构。

公开(公告)号：US09209038B2

公开(公告)日：2015-12-08

申请号：US14267959

申请日：2014-05-02

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jason Richard Cantone ,  Linus Jang ,  Ryan Ryoung-Han Kim

IPC: H01L21/00 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/3086 ,  H01L21/823431

Abstract: Methods for fabricating integrated circuits and for forming masks for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing a patternable structure having first and second regions and including upper and lower mandrel layers. The method etches upper mandrels from the upper mandrel layer in the first and second regions. The method includes forming first upper spacer structures having a first width adjacent upper mandrels in the first region and forming second upper spacer structures having a second width not equal to the first width adjacent upper mandrels in the second region. The method etches the lower mandrel layer using the first and second upper spacer structures as an etch mask to form lower mandrels. Further, the method includes forming spacers adjacent the lower mandrels and etching a material using the spacers as an etch mask to form variably spaced features.

Abstract translation: 提供了制造集成电路和形成用于制造集成电路的掩模的方法。 一种用于制造集成电路的示例性方法包括提供具有第一和第二区域并且包括上部和下部心轴层的可图案化结构。 该方法在第一和第二区域中从上心轴层蚀刻上心轴。 该方法包括形成在第一区域中具有与上心轴相邻的第一宽度的第一上间隔结构，并且形成第二上间隔结构，其具有不等于第二区中相邻上心轴的第一宽度的第二宽度。 该方法使用第一和第二上间隔结构蚀刻下心轴层作为蚀刻掩模以形成下心轴。 此外，该方法包括形成邻近下心轴的间隔物，并使用间隔物蚀刻材料作为蚀刻掩模以形成可变间隔的特征。

公开(公告)号：US20150270176A1

公开(公告)日：2015-09-24

申请号：US14219365

申请日：2014-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Ryan Ryoung-Han Kim

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/321 ,  H01L21/285 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/45

CPC classification number: H01L21/823475 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/53228 ,  H01L23/53257 ,  H01L27/088 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a layer of insulating material above first and second transistors, within the layer of insulating material, forming a set of initial device-level contacts for each of the first and second transistors, wherein each set of initial device-level contacts comprises a plurality of source/drain contacts and a gate contact, forming an initial local interconnect structure that is conductively coupled to one of the initial device-level contacts in each of the first and second transistors, and removing the initial local interconnect structure and portions, but not all, of the initial device-level contacts for each the first and second transistors. The method also includes forming a copper local interconnect structure and copper caps above the recessed device-level contacts.

Abstract translation: 一种方法包括在绝缘材料层内的第一和第二晶体管之上形成绝缘材料层，形成用于第一和第二晶体管中的每一个的一组初始器件级触点，其中每组初始器件级触点包括 多个源极/漏极触点和栅极接触，形成初始局部互连结构，其导电耦合到第一和第二晶体管中的每一个中的初始器件级触点之一，以及去除初始局部互连结构和部分， 但不是所有的第一和第二晶体管的初始器件级触点。 该方法还包括在凹入的器件级触点上方形成铜局部互连结构和铜帽。

公开(公告)号：US08796859B2

公开(公告)日：2014-08-05

申请号：US13953125

申请日：2013-07-29

Applicant: GlobalFoundries Inc.

Inventor： Ryan Ryoung-Han Kim

IPC: H01L29/40

CPC classification number: H01L23/5384 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multilayer interconnect structure is formed by, providing a substrate (40) having thereon a first dielectric (50, 27) for supporting a multi-layer interconnection (39) having lower conductor MN (22, 23), upper conductor MN+1 (34, 35), dielectric interlayer (DIL) (68) and interconnecting via conductor VN+1/N (36, 36′). The lower conductor MN (22, 23) has a first upper surface (61) located in a recess below a second upper surface (56) of the first dielectric (50, 27). The DIL (68) is formed above the first (61) and second (56) surfaces. A cavity (1263) is etched through the DIL (68) from a desired location (122) of the upper conductor MN+1 (34), exposing the first surface (61). The cavity (1263) is filled with a further electrical conductor (80) to form the upper conductor MN+1 (34) and the connecting via conductor VN+1/N (36, 36′) making electrical contact with the first upper surface (61). A critical dimension (32, 37) between others (23) of lower conductors MN (22, 23) and the via conductor VN+1/N (36, 36′) is lengthened. Leakage current and electro-migration there-between are reduced.

Abstract translation: 多层互连结构通过提供一种衬底（40）形成，衬底（40）上具有第一电介质（50,27），用于支撑具有下导体MN（22,23），上导体MN + 1（ 34,35），电介质中间层（DIL）（68），并通过导体VN + 1 / N（36,36'）互连。 下导体MN（22,23）具有位于第一电介质（50,27）的第二上表面（56）下方的凹部中的第一上表面（61）。 DIL（68）形成在第一（61）和第二（56）表面上方。 通过DIL（68）从上导体MN + 1（34）的期望位置（122）蚀刻空腔（1263），露出第一表面（61）。 空腔（1263）填充有另外的电导体（80）以形成上导体MN + 1（34），并且连接通孔导体VN + 1 / N（36,36'）与第一上表面 （61）。 下导体MN（22,23）和通孔导体VN + 1 / N（36,36'）的其他（23）之间的临界尺寸（32,37）被延长。 泄漏电流和电迁移减少。

公开(公告)号：US20190267387A1

公开(公告)日：2019-08-29

申请号：US15903203

申请日：2018-02-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong Lim ,  Ryan Ryoung-Han Kim

IPC: H01L27/11 ,  G11C8/14 ,  H01L23/522 ,  H01L23/50 ,  H01L27/105 ,  H01L21/48 ,  H01L21/768

Abstract: A memory cell includes vertical transistors including first and second pass gate (PG) transistors, first and second pull-up (PU1 and PU2) transistors, and first and second pull-down (PD1 and PD2) transistors. A first bottom electrode connects bottom source/drain (SD) regions of PU1 and PU2. A second bottom electrode connects bottom SD regions of PD1 and PD2. A first shared contact connects the top SD region of PU2 to the gate structure of PU1. A second shared contact connects the top SD region of PD1 to the gate structure of PD2. A first top electrode is connected to the top SD regions of PG1, PU1 and the second shared contact to define a first storage node of the memory cell. A second top electrode is connected to the top SD regions of PG2, PU2 and the first shared contact to define a second storage node of the memory cell.

公开(公告)号：US10153162B2

公开(公告)日：2018-12-11

申请号：US15284773

申请日：2016-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Ryoung-Han Kim ,  Wenhui Wang ,  Azat Latypov ,  Tamer Coskun, Jr. ,  Lei Sun

IPC: H01L21/306 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/66

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method includes providing a circuit structure layer over a substrate and at least one etch layer over the circuit structure layer, in the at least one etch layer patterning at least one primary pattern feature having at least one primary pattern feature dimension and at least one assist pattern feature having at least one assist pattern feature dimension, where the primary pattern feature dimension is greater than the assist pattern feature dimension, reducing the at least one primary pattern feature dimension and closing the assist pattern feature to form an etch pattern, and etching a circuit structure feature using the etch pattern.

公开(公告)号：US20170141211A1

公开(公告)日：2017-05-18

申请号：US15168690

申请日：2016-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Kwan-Yong Lim ,  Min Gyu Sung ,  Ryan Ryoung-Han Kim

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: One illustrative integrated circuit product disclosed herein includes, among other things, a plurality of FinFET devices, each of which comprises a gate structure comprising a high-k gate insulation material and at least one layer of metal, a single diffusion break (SDB) isolation structure positioned in a first trench defined in a semiconductor substrate between first and second active regions, the SDB isolation structure comprising the high-k insulating material and the at least one layer of metal, and a double diffusion break (DDB) isolation structure positioned in a second trench defined in a semiconductor substrate between third and fourth active regions, the DDB isolation structure comprising a first insulating material that substantially fills the second trench.

公开(公告)号：US09466604B2

公开(公告)日：2016-10-11

申请号：US14540724

申请日：2014-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Myungjun Lee ,  Ryan Ryoung-Han Kim ,  Jongwook Kye

IPC: H01L29/66 ,  H01L21/82 ,  H01L27/11 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/1104 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for utilizing metal segments of an additional metal layer as landing pads for vias and also as local interconnects between contacts in an IC device and resulting devices are disclosed. Embodiments include forming source/drain and gate contacts connected to transistors on a substrate in an integrated circuit device, each contact having an upper surface with a first area; forming metal segments in a plane at the upper surface of the contacts, each metal segment being in contact with one or more of the contacts and having a second area greater than the first area; and forming one or more vias between one or more of the metal segments and one or more first segments of a first metal layer.

Abstract translation: 公开了用于利用附加金属层的金属段作为通孔的着陆焊盘以及IC器件中的触点之间的局部互连以及所产生的器件的方法。 实施例包括在集成电路器件中形成连接到衬底上的晶体管的源极/漏极和栅极触点，每个触点具有带有第一区域的上表面; 在触头的上表面处的平面中形成金属段，每个金属段与一个或多个触点接触并具有大于第一区的第二区; 以及在一个或多个金属段和第一金属层的一个或多个第一段之间形成一个或多个通孔。