公开(公告)号：US09905460B2

公开(公告)日：2018-02-27

申请号：US14933650

申请日：2015-11-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Moosung M. Chae ,  Ki Young Lee ,  Songkram Srivathanakul

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76858 ,  H01L21/76867 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53209

Abstract: A method of forming a self-forming barrier includes selectively removing a portion of a semiconductor dielectric layer to form a three-dimensional pattern within a remaining portion of the dielectric layer. A metal liner layer is disposed on a surface of the pattern to provide a metal lined pattern. A metal filling is disposed over the metal lined pattern, the metal filling being at least partially composed of a metal used in the metal liner layer. Diffusion ions are disposed in one of the metal filling and the metal liner layer. Heat is applied to the metal filling and metal liner layer to diffuse the diffusion ions from one of the metal filling and the metal liner layer into the dielectric layer to form a barrier layer between the metal liner layer and the dielectric layer.

公开(公告)号：US09793169B1

公开(公告)日：2017-10-17

申请号：US15175187

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy Cao ,  Huang Liu ,  Guillaume Bouche ,  Songkram Srivathanakul

IPC: H01L21/02 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3115

CPC classification number: H01L21/823431 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3115 ,  H01L29/66795

Abstract: One method disclosed herein includes, among other things, forming a process layer on a substrate, forming a carbon-containing silicon dioxide layer above the process layer and forming a patterned mask layer above the carbon-containing silicon dioxide layer. The patterned mask layer exposes portions of the carbon-containing silicon dioxide layer. A material modification process is performed on the exposed portions of the carbon-containing silicon dioxide layer to generate modified portions, and the modified portions are removed. The process layer is etched using remaining portions of the carbon-containing silicon dioxide layer as an etch mask.

公开(公告)号：US09349814B2

公开(公告)日：2016-05-24

申请号：US14730887

申请日：2015-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang Chen ,  Hung-Wei Liu ,  Rohit Pal ,  Hsin-Neng Tai ,  Huey-Ming Wang ,  Tae Hoon Lee ,  Songkram Srivathanakul ,  Danni Chen

IPC: H01L29/76 ,  H01L29/423 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/42364 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092

Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

公开(公告)号：US09245979B2

公开(公告)日：2016-01-26

申请号：US13902369

申请日：2013-05-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Songkram Srivathanakul

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/7851

Abstract: FinFET semiconductor devices with local isolation features and methods for fabricating such devices are provided. In one embodiment, a method for fabricating a semiconductor device includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon, wherein each of the plurality of fin structures has sidewalls, forming spacers about the sidewalls of the plurality of fin structures, and forming a silicon-containing layer over the semiconductor substrate and in between the plurality of fin structures. The method further includes removing at least a first portion of the silicon-containing layer to form a plurality of void regions while leaving at least a second portion thereof in place and depositing an isolation material in the plurality of void regions.

Abstract translation: 提供具有局部隔离特征的FinFET半导体器件和用于制造这种器件的方法。 在一个实施例中，制造半导体器件的方法包括提供包括形成在其上的多个翅片结构的半导体衬底，其中，所述多个翅片结构中的每一个具有侧壁，围绕所述多个翅片结构的侧壁形成间隔件，以及形成 位于所述半导体衬底上并位于所述多个翅片结构之间的含硅层。 该方法还包括移除含硅层的至少第一部分以形成多个空隙区域，同时至少留下第二部分，并在多个空隙区域中沉积隔离材料。

公开(公告)号：US08940650B2

公开(公告)日：2015-01-27

申请号：US13787521

申请日：2013-03-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Huy Cao ,  Huang Liu ,  Hoong Shing Wong ,  Songkram Srivathanakul ,  Sandeep Gaan

IPC: H01L21/31 ,  H01L21/02

CPC classification number: H01L21/02274 ,  H01L21/0217

Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles.

Abstract translation: 一种制造集成电路的方法包括以下步骤：提供包括设置在其上的半导体器件的半导体衬底，并且使用第一沉积工艺在半导体衬底之上和半导体器件上沉积第一氮化硅层。 第一沉积工艺是在多个循环中操作的等离子体增强化学气相沉积（PECVD）工艺，每个循环具有第一时间间隔和第二时间间隔。 PECVD方法包括以下步骤：在第一时间间隔期间产生具有电源的等离子体，等离子体包括提供硅的气体和提供供给气体的反应性离子和自由基物质，并且在第二时间期间停止产生等离子体 间隔紧随着第一个时间间隔。 该方法还包括在多个循环之后在第一氮化硅层上沉积第二氮化硅层。

公开(公告)号：US20140346599A1

公开(公告)日：2014-11-27

申请号：US13902369

申请日：2013-05-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Songkram Srivathanakul

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/7851

Abstract: FinFET semiconductor devices with local isolation features and methods for fabricating such devices are provided. In one embodiment, a method for fabricating a semiconductor device includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon, wherein each of the plurality of fin structures has sidewalls, forming spacers about the sidewalls of the plurality of fin structures, and forming a silicon-containing layer over the semiconductor substrate and in between the plurality of fin structures. The method further includes removing at least a first portion of the silicon-containing layer to form a plurality of void regions while leaving at least a second portion thereof in place and depositing an isolation material in the plurality of void regions.

Abstract translation: 提供具有局部隔离特征的FinFET半导体器件和用于制造这种器件的方法。 在一个实施例中，制造半导体器件的方法包括提供包括形成在其上的多个翅片结构的半导体衬底，其中，所述多个翅片结构中的每一个具有侧壁，围绕所述多个鳍结构的侧壁形成间隔件，以及形成 位于所述半导体衬底上并位于所述多个翅片结构之间的含硅层。 该方法还包括移除含硅层的至少第一部分以形成多个空隙区域，同时至少留下第二部分，并在多个空隙区域中沉积隔离材料。

公开(公告)号：US20140256141A1

公开(公告)日：2014-09-11

申请号：US13787521

申请日：2013-03-06

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Huy Cao ,  Huang Liu ,  Hoong Shing Wong ,  Songkram Srivathanakul ,  Sandeep Gaan

IPC: H01L21/02

CPC classification number: H01L21/02274 ,  H01L21/0217

Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles.

Abstract translation: 一种制造集成电路的方法包括以下步骤：提供包括设置在其上的半导体器件的半导体衬底，并且使用第一沉积工艺在半导体衬底之上和半导体器件上沉积第一氮化硅层。 第一沉积工艺是在多个循环中操作的等离子体增强化学气相沉积（PECVD）工艺，每个循环具有第一时间间隔和第二时间间隔。 PECVD方法包括以下步骤：在第一时间间隔期间产生具有电源的等离子体，等离子体包括提供硅的气体和提供供给气体的反应性离子和自由基物质，并且在第二时间期间停止产生等离子体 间隔紧随着第一个时间间隔。 该方法还包括在多个循环之后在第一氮化硅层上沉积第二氮化硅层。